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📄 mux_gcb.tdf

📁 用VHDL写的计算器
💻 TDF
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=16 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 10 
SUBDESIGN mux_gcb
( 
	data[15..0]	:	input;
	result[0..0]	:	output;
	sel[3..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_ffs_wire[3..0]	: WIRE;
	sel_node[3..0]	: WIRE;
	w_data139w[3..0]	: WIRE;
	w_data140w[3..0]	: WIRE;
	w_data141w[3..0]	: WIRE;
	w_data142w[3..0]	: WIRE;
	w_data84w[15..0]	: WIRE;
	w_result134w	: WIRE;
	w_result135w	: WIRE;
	w_result136w	: WIRE;
	w_result137w	: WIRE;
	w_result138w	: WIRE;
	w_result148w	: WIRE;
	w_result149w	: WIRE;
	w_result169w	: WIRE;
	w_result170w	: WIRE;
	w_result186w	: WIRE;
	w_result187w	: WIRE;
	w_result203w	: WIRE;
	w_result204w	: WIRE;
	w_result220w	: WIRE;
	w_result85w	: WIRE;
	w_sel143w[1..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result85w);
	sel_ffs_wire[] = ( sel[3..0]);
	sel_node[] = ( sel_ffs_wire[3..2], sel[1..0]);
	w_data139w[3..0] = w_data84w[3..0];
	w_data140w[3..0] = w_data84w[7..4];
	w_data141w[3..0] = w_data84w[11..8];
	w_data142w[3..0] = w_data84w[15..12];
	w_data84w[] = ( data[15..0]);
	w_result134w = (((w_result136w & sel_node[2..2]) & (! w_result220w)) # (w_result220w & (w_result138w # (! sel_node[2..2]))));
	w_result135w = w_result148w;
	w_result136w = w_result169w;
	w_result137w = w_result186w;
	w_result138w = w_result203w;
	w_result148w = (((w_data139w[1..1] & w_sel143w[0..0]) & (! w_result149w)) # (w_result149w & (w_data139w[3..3] # (! w_sel143w[0..0]))));
	w_result149w = (((w_data139w[0..0] & (! w_sel143w[1..1])) & (! w_sel143w[0..0])) # (w_sel143w[1..1] & (w_sel143w[0..0] # w_data139w[2..2])));
	w_result169w = (((w_data140w[1..1] & w_sel143w[0..0]) & (! w_result170w)) # (w_result170w & (w_data140w[3..3] # (! w_sel143w[0..0]))));
	w_result170w = (((w_data140w[0..0] & (! w_sel143w[1..1])) & (! w_sel143w[0..0])) # (w_sel143w[1..1] & (w_sel143w[0..0] # w_data140w[2..2])));
	w_result186w = (((w_data141w[1..1] & w_sel143w[0..0]) & (! w_result187w)) # (w_result187w & (w_data141w[3..3] # (! w_sel143w[0..0]))));
	w_result187w = (((w_data141w[0..0] & (! w_sel143w[1..1])) & (! w_sel143w[0..0])) # (w_sel143w[1..1] & (w_sel143w[0..0] # w_data141w[2..2])));
	w_result203w = (((w_data142w[1..1] & w_sel143w[0..0]) & (! w_result204w)) # (w_result204w & (w_data142w[3..3] # (! w_sel143w[0..0]))));
	w_result204w = (((w_data142w[0..0] & (! w_sel143w[1..1])) & (! w_sel143w[0..0])) # (w_sel143w[1..1] & (w_sel143w[0..0] # w_data142w[2..2])));
	w_result220w = (((w_result135w & (! sel_node[3..3])) & (! sel_node[2..2])) # (sel_node[3..3] & (sel_node[2..2] # w_result137w)));
	w_result85w = w_result134w;
	w_sel143w[1..0] = sel_node[1..0];
END;
--VALID FILE

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