f_adder.vhd

来自「用VHDL写的计算器」· VHDL 代码 · 共 11 行

library ieee;
use ieee.std_logic_1164.all;
entity f_adder is
port(ain,bin,cin: IN std_logic;
cout,sum:OUT std_logic);
end f_adder;
architecture fd of f_adder is
begin
sum<= ain xor bin xor cin;
cout<= ((ain and bin) or (ain and cin) or (bin and cin));
end architecture fd;