cal.vhd

用VHDL写的计算器

library ieee;
use ieee.std_logic_1164.all;
ENTITY cal IS
PORT ( 
         clk,reset,enable: in std_logic;
         DATAIN:           IN STD_LOGIC_vector(3 downto 0); 
         Q :               OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END cal;
ARCHITECTURE behav OF cal IS
component bcd is
port(
     SAa, SAb: in std_logic_vector(3 downto 0);
     operator: in std_logic;
     sum: out std_logic_vector(7 downto 0) );
end component;
TYPE states IS (st0, st1, st2, st3,st4);      
SIGNAL STX : states  ;
signal va,vb:std_logic_vector(3 downto 0);
signal opin:std_logic;
signal op:std_logic_vector(3 downto 0);
signal tempsum:std_logic_vector(7 downto 0);
signal tempQ:std_logic_vector(23 downto 0);  
BEGIN                          
    COMREG : PROCESS(CLK,RESET)  
             BEGIN 
                IF RESET ='1' 
                THEN    STX <= ST0;
    ELSIF CLK'EVENT AND CLK = '1' THEN    CASE STX IS           
        WHEN st0 => IF ((not datain(3)) or ((not datain(2) and (not datain(1)))))='1' and enable='1' THEN  
        STX <= st1;
        va<=datain; 
        else
        va<="1111";
        END IF;
        WHEN st1 => IF DATAIN = "1010"  and enable='1'
        THEN STX <= st2;
             opin<='0';
             op<=datain;
        elsif datain="1011" and enable='1'
        then STX<=st2;
             opin<='1';
             op<=datain;
        elsif  ((not datain(3)) or ((not datain(2) and (not datain(1)))))='1' and enable='1'
        THEN va<=datain;
        else 
           op<="1111";
        end if;
        WHEN st2 => IF ((not datain(3)) or ((not datain(2) and (not datain(1)))))='1' and enable='1' 
        THEN  STX <= st3;
              vb<=datain; 
            elsif datain="1010" and enable='1' then
            opin<='0';
            op<=datain;
            elsif datain="1011" and enable='1' then
            opin<='1';
            op<=datain;
            else vb<="1111";    
            END IF;
        WHEN st3=>  IF DATAIN = "1100" and enable ='1' 
        THEN  STX <= st4;
                    elsif ((not datain(3)) or ((not datain(2) and (not datain(1)))))='1' and enable='1' then
              vb<=datain; 
        END IF;
        WHEN st4=>  IF DATAIN = "1101" and enable='1' 
        THEN  STX <= st0;
        END IF;
        WHEN OTHERS => STX <= st0; 
     END CASE ;
   END IF;
END PROCESS COMREG ;
u1:bcd PORT MAP(SAa=>va,SAb=>vb,operator=>opin,sum=>tempsum);
COM1: PROCESS(STX,va,vb,op,tempsum) 
BEGIN 
  CASE STX IS           
    WHEN st0 => 
     tempQ<="111111111111111111111111" ; 
    WHEN st1 =>    
     tempQ(23 downto 20)<=va;
     tempQ(19 downto 0)<="11111111111111111111";                
    WHEN st2 => 
     tempQ(23 downto 20)<=va;
     tempQ(19 downto 16)<=op;
     tempQ(15 downto 0)<="1111111111111111";
    WHEN st3=>  
     tempQ(23 downto 20)<=va;
     tempQ(19 downto 16)<=op;
     tempQ(15 downto 12)<=vb;
     tempQ(11 downto 0)<="111111111111";    
    WHEN st4=> 
     tempQ(23 downto 20)<=va;
     tempQ(19 downto 16)<=op;
     tempQ(15 downto 12)<=vb;
     tempQ(11 downto 8)<="1100";
     tempQ(7 downto 0)<=tempsum;
    WHEN OTHERS => tempQ <= "111111111111111111111111";                                                
  END CASE ;
END PROCESS COM1 ;
Q<=tempQ;
END behav;