vgainterface.vhd

用VHDL写的计算器

library IEEE;
use IEEE.std_logic_1164.all;  
use IEEE.std_logic_unsigned.all;
--use IEEE.std_logic_arith.all;

entity VgaInterface is
 port(
  reset                :         in  STD_LOGIC;
  clk_0                :         in  STD_LOGIC;
  ----  These are the Signals connect with CalControl
  pid_vga_data         :         in  STD_LOGIC_VECTOR(23 downto 0);
  ----  These are the VGA Control Signal
  pod_vga_r            :         out STD_LOGIC;
  pod_vga_g            :         out STD_LOGIC;
  pod_vga_b            :         out STD_LOGIC;
  pod_vga_hs           :         out STD_LOGIC;
  pod_vga_vs           :         out STD_LOGIC
);
end VgaInterface;

architecture behavior of VgaInterface is
signal vga_data : std_logic_vector(23 downto 0);
signal clk : std_logic:='0';
signal vga_r : std_logic;
signal vga_g : std_logic;
signal vga_b : std_logic;
signal vga_hs : std_logic;
signal vga_vs : std_logic;
signal hs_p : std_logic;
signal vs_p : std_logic;

signal enable : std_logic;
signal vector_x : std_logic_vector(9 downto 0);
signal vector_y : std_logic_vector(8 downto 0);
signal char_data : std_logic_vector(0 downto 0);
signal char_address : std_logic_vector(15 downto 0);
component vga
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
	);
end component;

begin
u1:vga port map(address => char_address, clock => clk, q => char_data);
 process(clk_0)
    begin
        if(clk_0'event and clk_0='1') then 
             clk <= not clk;
        end if;
 end process;
process(clk,reset)
 begin
  if reset='1' then
   vga_data <= (others=>'0');
  elsif clk'event and clk='1' then
   vga_data <= pid_vga_data;
  end if;
 end process;
  
 process(clk,reset)
 begin
  if reset='1' then
   vector_x <= (others=>'0');
  elsif clk'event and clk='1' then
   if vector_x=799 then
    vector_x <= (others=>'0');
   else
    vector_x <= vector_x + 1;
   end if;
  end if;
 end process;

 process(clk,reset)
 begin
  if reset='1' then
   vector_y <= (others=>'0');
  elsif clk'event and clk='1' then
   if vector_x=799 then
    if vector_y=524 then
     vector_y <= (others=>'0');
    else
     vector_y <= vector_y + 1;
    end if;
   end if;
  end if;
 end process;

 process(clk,reset)
 begin
  if clk'event and clk='1' then
    char_address <= (others => '0');
	char_address(4 downto 0) <= vector_x(4 downto 0);
	char_address(9 downto 5) <= vector_y(4 downto 0);
  if vector_x <= 231 and vector_x >=200 and vector_y <= 131 and vector_y >=100  then
	char_address(13 downto 10) <= vga_data(23 downto 20);
  elsif vector_x <= 263 and vector_x >=232 and vector_y <= 131 and vector_y >= 100 then
	char_address(13 downto 10) <= vga_data(19 downto 16);
  elsif vector_x <= 295 and vector_x >=264 and vector_y <= 131 and vector_y >=100 then
	char_address(13 downto 10) <= vga_data(15 downto 12);
  elsif vector_x <= 327 and vector_x >=296 and vector_y <= 131 and vector_y >= 100 then
	char_address(13 downto 10) <= vga_data(11 downto 8);
  elsif vector_x <= 359 and vector_x >=328 and vector_y <= 131 and vector_y >= 100 then
	char_address(13 downto 10) <= vga_data(7 downto 4);
  elsif vector_x <= 391 and vector_x >=360 and vector_y <= 131 and vector_y >= 100 then
	char_address(13 downto 10) <= vga_data(3 downto 0);
  else 
    char_address <= (others => '0');
  end if;
 end if;
 end process;

 process(clk,reset)
 begin
  if clk'event and clk='1' then
	vga_r <= char_data(0) ;
	vga_g <= char_data(0) ;
	vga_b <= char_data(0) ;
  end if;
 end process;
  
 process(clk,reset)
 begin
  if reset='1' then
   hs_p <= '1';
  elsif clk'event and clk='1' then
   if vector_x>=656 and vector_x<752 then
    hs_p <= '0';
   else
    hs_p <= '1';
   end if;
  end if;
 end process;
 
 process(clk,reset)
 begin
  if reset='1' then
   vs_p <= '1';
  elsif clk'event and clk='1' then
   if vector_y>=490 and vector_y<492 then
    vs_p <= '0';
   else
    vs_p <= '1';
   end if;
  end if;
 end process;
   
 process(clk)
 begin
  if(clk'event and clk='1')then
   if (vector_x>=640 or vector_y>=480)then
    enable <= '0';
   else 
    enable <= '1';
   end if;
  end if;
 end process;

 
 process(clk,reset)
 begin
  if reset='1' then
   pod_vga_r <= '0';
  elsif clk'event and clk='1' then
   pod_vga_r <= vga_r and enable;
  end if;
 end process;
 
 process(clk,reset)
 begin
  if reset='1' then
   pod_vga_g <= '0';
  elsif clk'event and clk='1' then
   pod_vga_g <= vga_g and enable;
  end if;
 end process;
 
 process(clk,reset)
 begin
  if reset='1' then
   pod_vga_b <= '0';
  elsif clk'event and clk='1' then
   pod_vga_b <= vga_b and enable;
  end if;
 end process;
 
 process(clk,reset)
 begin
  if reset='1' then
   pod_vga_hs <= '0';
  elsif clk'event and clk='1' then
   pod_vga_hs <=  hs_p;
  end if;
 end process;
 
 process(clk,reset)
 begin
  if reset='1' then
   pod_vga_vs <= '0';
  elsif clk'event and clk='1' then
   pod_vga_vs <=  vs_p;
  end if;
 end process;
end behavior;