ivga.qsf

用VHDL写的计算器

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		Ivga_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:31:12  MAY 11, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name VHDL_FILE Ivga.vhd
set_global_assignment -name VHDL_FILE vgainterface.vhd
set_global_assignment -name VHDL_FILE cal.vhd
set_global_assignment -name VHDL_FILE bcd.vhd
set_global_assignment -name VHDL_FILE bcd4adder.vhd
set_global_assignment -name VHDL_FILE BCD4suber.vhd
set_global_assignment -name VHDL_FILE Complementor.vhd
set_global_assignment -name VHDL_FILE F4a_adder.vhd
set_global_assignment -name VHDL_FILE f_adder.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE Ivga.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_233 -to DATA[0]
set_location_assignment PIN_234 -to DATA[1]
set_location_assignment PIN_235 -to DATA[2]
set_location_assignment PIN_236 -to DATA[3]
set_location_assignment PIN_240 -to En
set_location_assignment PIN_239 -to reset
set_location_assignment PIN_152 -to clk_vga
set_location_assignment PIN_226 -to Ovga_r
set_location_assignment PIN_225 -to Ovga_g
set_location_assignment PIN_223 -to Ovga_b
set_location_assignment PIN_222 -to Ovga_hs
set_location_assignment PIN_219 -to Ovga_vs

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY Ivga

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE FUNCTIONAL