ivga.map.eqn

用VHDL写的计算器

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--C1_pod_vga_r is VgaInterface:u2|pod_vga_r
--operation mode is normal

C1_pod_vga_r_lut_out = C1_vga_r & C1_enable;
C1_pod_vga_r = DFFEAS(C1_pod_vga_r_lut_out, C1_clk, !reset, , , , , , );


--C1_pod_vga_hs is VgaInterface:u2|pod_vga_hs
--operation mode is normal

C1_pod_vga_hs_lut_out = !C1_hs_p;
C1_pod_vga_hs = DFFEAS(C1_pod_vga_hs_lut_out, C1_clk, !reset, , , , , , );


--C1_pod_vga_vs is VgaInterface:u2|pod_vga_vs
--operation mode is normal

C1_pod_vga_vs_lut_out = !C1_vs_p;
C1_pod_vga_vs = DFFEAS(C1_pod_vga_vs_lut_out, C1_clk, !reset, , , , , , );


--C1_vga_r is VgaInterface:u2|vga_r
--operation mode is normal

C1_vga_r_lut_out = M1_address_reg_a[4] & (N1L1 & (M1_ram_block1a3) # !N1L1 & M1_ram_block1a1) # !M1_address_reg_a[4] & (N1L1);
C1_vga_r = DFFEAS(C1_vga_r_lut_out, C1_clk, VCC, , , , , , );


--C1_enable is VgaInterface:u2|enable
--operation mode is normal

C1_enable_lut_out = !C1L401 & (!C1_vector_x[8] & !C1_vector_x[7] # !C1_vector_x[9]);
C1_enable = DFFEAS(C1_enable_lut_out, C1_clk, VCC, , , , , , );


--C1_clk is VgaInterface:u2|clk
--operation mode is normal

C1_clk_lut_out = !C1_clk;
C1_clk = DFFEAS(C1_clk_lut_out, clk_vga, VCC, , , , , , );


--C1_hs_p is VgaInterface:u2|hs_p
--operation mode is normal

C1_hs_p_lut_out = C1_vector_x[7] & !C1_vector_x[8] & C1_vector_x[9] & C1L17;
C1_hs_p = DFFEAS(C1_hs_p_lut_out, C1_clk, !reset, , , , , , );


--C1_vs_p is VgaInterface:u2|vs_p
--operation mode is normal

C1_vs_p_lut_out = C1_vector_y[1] & C1_vector_y[3] & C1L401 & C1L05;
C1_vs_p = DFFEAS(C1_vs_p_lut_out, C1_clk, !reset, , , , , , );


--M1_ram_block1a1 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|ram_block1a1
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
M1_ram_block1a1_PORT_A_address = BUS(C1_char_address[0], C1_char_address[1], C1_char_address[2], C1_char_address[3], C1_char_address[4], C1_char_address[5], C1_char_address[6], C1_char_address[7], C1_char_address[8], C1_char_address[9], C1_char_address[10], C1_char_address[11]);
M1_ram_block1a1_PORT_A_address_reg = DFFE(M1_ram_block1a1_PORT_A_address, M1_ram_block1a1_clock_0, , , );
M1_ram_block1a1_clock_0 = C1_clk;
M1_ram_block1a1_PORT_A_data_out = MEMORY(, , M1_ram_block1a1_PORT_A_address_reg, , , , , , M1_ram_block1a1_clock_0, , , , , );
M1_ram_block1a1_PORT_A_data_out_reg = DFFE(M1_ram_block1a1_PORT_A_data_out, M1_ram_block1a1_clock_0, , , );
M1_ram_block1a1 = M1_ram_block1a1_PORT_A_data_out_reg[0];


--M1_address_reg_a[4] is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|address_reg_a[4]
--operation mode is normal

M1_address_reg_a[4]_lut_out = M1_address_reg_a[0];
M1_address_reg_a[4] = DFFEAS(M1_address_reg_a[4]_lut_out, C1_clk, VCC, , , , , , );


--M1_ram_block1a2 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|ram_block1a2
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
M1_ram_block1a2_PORT_A_address = BUS(C1_char_address[0], C1_char_address[1], C1_char_address[2], C1_char_address[3], C1_char_address[4], C1_char_address[5], C1_char_address[6], C1_char_address[7], C1_char_address[8], C1_char_address[9], C1_char_address[10], C1_char_address[11]);
M1_ram_block1a2_PORT_A_address_reg = DFFE(M1_ram_block1a2_PORT_A_address, M1_ram_block1a2_clock_0, , , );
M1_ram_block1a2_clock_0 = C1_clk;
M1_ram_block1a2_PORT_A_data_out = MEMORY(, , M1_ram_block1a2_PORT_A_address_reg, , , , , , M1_ram_block1a2_clock_0, , , , , );
M1_ram_block1a2_PORT_A_data_out_reg = DFFE(M1_ram_block1a2_PORT_A_data_out, M1_ram_block1a2_clock_0, , , );
M1_ram_block1a2 = M1_ram_block1a2_PORT_A_data_out_reg[0];


--M1_address_reg_a[5] is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|address_reg_a[5]
--operation mode is normal

M1_address_reg_a[5]_lut_out = M1_address_reg_a[1];
M1_address_reg_a[5] = DFFEAS(M1_address_reg_a[5]_lut_out, C1_clk, VCC, , , , , , );


--M1_ram_block1a0 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|ram_block1a0
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
M1_ram_block1a0_PORT_A_address = BUS(C1_char_address[0], C1_char_address[1], C1_char_address[2], C1_char_address[3], C1_char_address[4], C1_char_address[5], C1_char_address[6], C1_char_address[7], C1_char_address[8], C1_char_address[9], C1_char_address[10], C1_char_address[11]);
M1_ram_block1a0_PORT_A_address_reg = DFFE(M1_ram_block1a0_PORT_A_address, M1_ram_block1a0_clock_0, , , );
M1_ram_block1a0_clock_0 = C1_clk;
M1_ram_block1a0_PORT_A_data_out = MEMORY(, , M1_ram_block1a0_PORT_A_address_reg, , , , , , M1_ram_block1a0_clock_0, , , , , );
M1_ram_block1a0_PORT_A_data_out_reg = DFFE(M1_ram_block1a0_PORT_A_data_out, M1_ram_block1a0_clock_0, , , );
M1_ram_block1a0 = M1_ram_block1a0_PORT_A_data_out_reg[0];


--N1L1 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|mux_gcb:mux2|w_result148w~44
--operation mode is normal

N1L1 = M1_address_reg_a[4] & (M1_address_reg_a[5]) # !M1_address_reg_a[4] & (M1_address_reg_a[5] & M1_ram_block1a2 # !M1_address_reg_a[5] & (M1_ram_block1a0));


--M1_ram_block1a3 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|ram_block1a3
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
M1_ram_block1a3_PORT_A_address = BUS(C1_char_address[0], C1_char_address[1], C1_char_address[2], C1_char_address[3], C1_char_address[4], C1_char_address[5], C1_char_address[6], C1_char_address[7], C1_char_address[8], C1_char_address[9], C1_char_address[10], C1_char_address[11]);
M1_ram_block1a3_PORT_A_address_reg = DFFE(M1_ram_block1a3_PORT_A_address, M1_ram_block1a3_clock_0, , , );
M1_ram_block1a3_clock_0 = C1_clk;
M1_ram_block1a3_PORT_A_data_out = MEMORY(, , M1_ram_block1a3_PORT_A_address_reg, , , , , , M1_ram_block1a3_clock_0, , , , , );
M1_ram_block1a3_PORT_A_data_out_reg = DFFE(M1_ram_block1a3_PORT_A_data_out, M1_ram_block1a3_clock_0, , , );
M1_ram_block1a3 = M1_ram_block1a3_PORT_A_data_out_reg[0];


--C1_vector_y[5] is VgaInterface:u2|vector_y[5]
--operation mode is arithmetic

C1_vector_y[5]_carry_eqn = C1L69;
C1_vector_y[5]_lut_out = C1_vector_y[5] $ (C1_vector_y[5]_carry_eqn);
C1_vector_y[5] = DFFEAS(C1_vector_y[5]_lut_out, C1_clk, !reset, , C1L47, , , , );

--C1L89 is VgaInterface:u2|vector_y[5]~206
--operation mode is arithmetic

C1L89 = CARRY(!C1L69 # !C1_vector_y[5]);


--C1_vector_y[7] is VgaInterface:u2|vector_y[7]
--operation mode is arithmetic

C1_vector_y[7]_carry_eqn = C1L001;
C1_vector_y[7]_lut_out = C1_vector_y[7] $ (C1_vector_y[7]_carry_eqn);
C1_vector_y[7] = DFFEAS(C1_vector_y[7]_lut_out, C1_clk, !reset, , C1L47, , , , );

--C1L201 is VgaInterface:u2|vector_y[7]~210
--operation mode is arithmetic

C1L201 = CARRY(!C1L001 # !C1_vector_y[7]);


--C1_vector_y[6] is VgaInterface:u2|vector_y[6]
--operation mode is arithmetic

C1_vector_y[6]_carry_eqn = C1L89;
C1_vector_y[6]_lut_out = C1_vector_y[6] $ (!C1_vector_y[6]_carry_eqn);
C1_vector_y[6] = DFFEAS(C1_vector_y[6]_lut_out, C1_clk, !reset, , C1L47, , , , );

--C1L001 is VgaInterface:u2|vector_y[6]~214
--operation mode is arithmetic

C1L001 = CARRY(C1_vector_y[6] & (!C1L89));


--C1_vector_y[8] is VgaInterface:u2|vector_y[8]
--operation mode is normal

C1_vector_y[8]_carry_eqn = C1L201;
C1_vector_y[8]_lut_out = C1_vector_y[8] $ (!C1_vector_y[8]_carry_eqn);
C1_vector_y[8] = DFFEAS(C1_vector_y[8]_lut_out, C1_clk, !reset, , C1L47, , , , );


--C1L401 is VgaInterface:u2|vector_y[8]~221
--operation mode is normal

C1L401 = C1_vector_y[5] & C1_vector_y[7] & C1_vector_y[6] & C1_vector_y[8];


--C1_vector_x[9] is VgaInterface:u2|vector_x[9]
--operation mode is normal

C1_vector_x[9]_lut_out = C1L1 & !C1L47;
C1_vector_x[9] = DFFEAS(C1_vector_x[9]_lut_out, C1_clk, !reset, , , , , , );


--C1_vector_x[8] is VgaInterface:u2|vector_x[8]
--operation mode is normal

C1_vector_x[8]_lut_out = C1L2 & !C1L47;
C1_vector_x[8] = DFFEAS(C1_vector_x[8]_lut_out, C1_clk, !reset, , , , , , );


--C1_vector_x[7] is VgaInterface:u2|vector_x[7]
--operation mode is normal

C1_vector_x[7]_lut_out = C1L4;
C1_vector_x[7] = DFFEAS(C1_vector_x[7]_lut_out, C1_clk, !reset, , , , , , );


--C1L75 is VgaInterface:u2|process4~710
--operation mode is normal

C1L75 = C1_vector_x[7] & (!C1_vector_x[8]);


--C1_vector_x[6] is VgaInterface:u2|vector_x[6]
--operation mode is normal

C1_vector_x[6]_lut_out = C1L6;
C1_vector_x[6] = DFFEAS(C1_vector_x[6]_lut_out, C1_clk, !reset, , , , , , );


--C1_vector_x[5] is VgaInterface:u2|vector_x[5]
--operation mode is normal

C1_vector_x[5]_lut_out = C1L8 & !C1L47;
C1_vector_x[5] = DFFEAS(C1_vector_x[5]_lut_out, C1_clk, !reset, , , , , , );


--C1_vector_x[4] is VgaInterface:u2|vector_x[4]
--operation mode is normal

C1_vector_x[4]_lut_out = C1L01;
C1_vector_x[4] = DFFEAS(C1_vector_x[4]_lut_out, C1_clk, !reset, , , , , , );


--C1L17 is VgaInterface:u2|process6~49
--operation mode is normal

C1L17 = C1_vector_x[6] & (!C1_vector_x[4] # !C1_vector_x[5]) # !C1_vector_x[6] & (C1_vector_x[5] # C1_vector_x[4]);


--C1_vector_y[1] is VgaInterface:u2|vector_y[1]
--operation mode is arithmetic

C1_vector_y[1]_carry_eqn = C1L88;
C1_vector_y[1]_lut_out = C1_vector_y[1] $ (C1_vector_y[1]_carry_eqn);
C1_vector_y[1] = DFFEAS(C1_vector_y[1]_lut_out, C1_clk, !reset, , C1L47, , , , );

--C1L09 is VgaInterface:u2|vector_y[1]~223
--operation mode is arithmetic

C1L09 = CARRY(!C1L88 # !C1_vector_y[1]);


--C1_vector_y[3] is VgaInterface:u2|vector_y[3]
--operation mode is arithmetic

C1_vector_y[3]_carry_eqn = C1L29;
C1_vector_y[3]_lut_out = C1_vector_y[3] $ (C1_vector_y[3]_carry_eqn);
C1_vector_y[3] = DFFEAS(C1_vector_y[3]_lut_out, C1_clk, !reset, , C1L47, , , , );

--C1L49 is VgaInterface:u2|vector_y[3]~227
--operation mode is arithmetic

C1L49 = CARRY(!C1L29 # !C1_vector_y[3]);


--C1_vector_y[2] is VgaInterface:u2|vector_y[2]
--operation mode is arithmetic

C1_vector_y[2]_carry_eqn = C1L09;
C1_vector_y[2]_lut_out = C1_vector_y[2] $ (!C1_vector_y[2]_carry_eqn);
C1_vector_y[2] = DFFEAS(C1_vector_y[2]_lut_out, C1_clk, !reset, , C1L47, , , , );

--C1L29 is VgaInterface:u2|vector_y[2]~231
--operation mode is arithmetic

C1L29 = CARRY(C1_vector_y[2] & (!C1L09));


--C1_vector_y[4] is VgaInterface:u2|vector_y[4]
--operation mode is arithmetic

C1_vector_y[4]_carry_eqn = C1L49;
C1_vector_y[4]_lut_out = C1_vector_y[4] $ (!C1_vector_y[4]_carry_eqn);
C1_vector_y[4] = DFFEAS(C1_vector_y[4]_lut_out, C1_clk, !reset, , C1L47, , , , );

--C1L69 is VgaInterface:u2|vector_y[4]~235
--operation mode is arithmetic

C1L69 = CARRY(C1_vector_y[4] & (!C1L49));


--C1L05 is VgaInterface:u2|LessThan~1777
--operation mode is normal

C1L05 = !C1_vector_y[2] & !C1_vector_y[4];


--C1_char_address[0] is VgaInterface:u2|char_address[0]
--operation mode is normal

C1_char_address[0]_lut_out = C1_vector_x[0] & (C1L36 # !C1L63);
C1_char_address[0] = DFFEAS(C1_char_address[0]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[1] is VgaInterface:u2|char_address[1]
--operation mode is normal

C1_char_address[1]_lut_out = C1_vector_x[1] & (C1L36 # !C1L63);
C1_char_address[1] = DFFEAS(C1_char_address[1]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[2] is VgaInterface:u2|char_address[2]
--operation mode is normal

C1_char_address[2]_lut_out = C1_vector_x[2] & (C1L36 # !C1L63);
C1_char_address[2] = DFFEAS(C1_char_address[2]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[3] is VgaInterface:u2|char_address[3]
--operation mode is normal

C1_char_address[3]_lut_out = C1_vector_x[3] & (C1L36 # !C1L63);
C1_char_address[3] = DFFEAS(C1_char_address[3]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[4] is VgaInterface:u2|char_address[4]
--operation mode is normal

C1_char_address[4]_lut_out = C1_vector_x[4] & (C1L36 # !C1L63);
C1_char_address[4] = DFFEAS(C1_char_address[4]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[5] is VgaInterface:u2|char_address[5]
--operation mode is normal

C1_char_address[5]_lut_out = C1_vector_y[0] & (C1L36 # !C1L63);
C1_char_address[5] = DFFEAS(C1_char_address[5]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[6] is VgaInterface:u2|char_address[6]
--operation mode is normal

C1_char_address[6]_lut_out = C1_vector_y[1] & (C1L36 # !C1L63);
C1_char_address[6] = DFFEAS(C1_char_address[6]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[7] is VgaInterface:u2|char_address[7]
--operation mode is normal

C1_char_address[7]_lut_out = C1_vector_y[2] & (C1L36 # !C1L63);
C1_char_address[7] = DFFEAS(C1_char_address[7]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[8] is VgaInterface:u2|char_address[8]
--operation mode is normal

C1_char_address[8]_lut_out = C1_vector_y[3] & (C1L36 # !C1L63);
C1_char_address[8] = DFFEAS(C1_char_address[8]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[9] is VgaInterface:u2|char_address[9]
--operation mode is normal

C1_char_address[9]_lut_out = C1_vector_y[4] & (C1L36 # !C1L63);
C1_char_address[9] = DFFEAS(C1_char_address[9]_lut_out, C1_clk, VCC, , , , , , );


--C1_char_address[10] is VgaInterface:u2|char_address[10]
--operation mode is normal

C1_char_address[10]_lut_out = C1L07 & (C1_vga_data[16]) # !C1L07 & C1L04;
C1_char_address[10] = DFFEAS(C1_char_address[10]_lut_out, C1_clk, VCC, , , C1_vga_data[20], , C1L83, C1L86);


--C1_char_address[11] is VgaInterface:u2|char_address[11]
--operation mode is normal

C1_char_address[11]_lut_out = C1L07 & (C1_vga_data[17]) # !C1L07 & C1L24;
C1_char_address[11] = DFFEAS(C1_char_address[11]_lut_out, C1_clk, VCC, , , C1_vga_data[21], , C1L83, C1L86);


--M1_address_reg_a[0] is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|address_reg_a[0]
--operation mode is normal

M1_address_reg_a[0]_lut_out = C1_char_address[12];
M1_address_reg_a[0] = DFFEAS(M1_address_reg_a[0]_lut_out, C1_clk, VCC, , , , , , );


--M1_address_reg_a[1] is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|address_reg_a[1]
--operation mode is normal

M1_address_reg_a[1]_lut_out = C1_char_address[13];
M1_address_reg_a[1] = DFFEAS(M1_address_reg_a[1]_lut_out, C1_clk, VCC, , , , , , );


--C1_vector_x[3] is VgaInterface:u2|vector_x[3]
--operation mode is normal

C1_vector_x[3]_lut_out = C1L21;
C1_vector_x[3] = DFFEAS(C1_vector_x[3]_lut_out, C1_clk, !reset, , , , , , );


--C1_vector_x[2] is VgaInterface:u2|vector_x[2]
--operation mode is normal

C1_vector_x[2]_lut_out = C1L41;
C1_vector_x[2] = DFFEAS(C1_vector_x[2]_lut_out, C1_clk, !reset, , , , , , );


--C1L27 is VgaInterface:u2|reduce_nor~48
--operation mode is normal

C1L27 = C1_vector_x[5] # !C1_vector_x[2] # !C1_vector_x[3] # !C1_vector_x[4];


--C1_vector_x[1] is VgaInterface:u2|vector_x[1]
--operation mode is normal

C1_vector_x[1]_lut_out = C1L61;
C1_vector_x[1] = DFFEAS(C1_vector_x[1]_lut_out, C1_clk, !reset, , , , , , );


--C1_vector_x[0] is VgaInterface:u2|vector_x[0]
--operation mode is normal

C1_vector_x[0]_lut_out = C1L81;
C1_vector_x[0] = DFFEAS(C1_vector_x[0]_lut_out, C1_clk, !reset, , , , , , );


--C1L37 is VgaInterface:u2|reduce_nor~49
--operation mode is normal

C1L37 = !C1_vector_x[0] # !C1_vector_x[1];


--C1L85 is VgaInterface:u2|process4~711
--operation mode is normal

C1L85 = C1_vector_x[8] & (!C1_vector_x[7] & !C1_vector_x[6]);