bcd4adder.vhd

用VHDL写的计算器

library ieee;
use ieee.std_logic_1164.all;

entity BCD4Adder is
port(BCDa, BCDb: in std_logic_vector(3 downto 0);
    BCDs: out std_logic_vector(3 downto 0);
    BCDcarry: out std_logic );
end entity;

architecture Impl of BCD4Adder is
  component F4a_adder
	port(a, b: in std_logic_vector(3 downto 0);
    	s: out std_logic_vector(3 downto 0);
   		carry: out std_logic );
  end component;

signal zero:std_logic;
signal tmpc1, tmpc2: std_logic; 
signal tmp:std_logic_vector(3 downto 0); 
signal six:std_logic_vector(3 downto 0); 

begin
zero<='0';
  u1: F4a_adder port map
    (a=>BCDa, b=>BCDb, s=>tmp, carry=>tmpc1);
	tmpc2<=tmpc1 or ((tmp(3) and tmp(1))or(tmp(3) and tmp(2)));
	six(0)<=zero;
	six(3)<=zero;
	six(1)<=tmpc2;
	six(2)<=tmpc2;
	BCDcarry<=tmpc2;
  u2: F4a_adder port map
    (a=>six, b=>tmp, s=>BCDs); 
end architecture Impl;