ivga.map.summary

来自「用VHDL写的计算器」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Thu May 11 13:23:41 2006
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : Ivga
Top-level Entity Name : Ivga
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 170
Total pins : 12
Total virtual pins : 0
Total memory bits : 16,384
Total PLLs : 0