bcd.vhd

用VHDL写的计算器

library ieee;
use ieee.std_logic_1164.all;

entity bcd is
port(SAa, SAb: in std_logic_vector(3 downto 0);
    operator: in std_logic;
    sum: out std_logic_vector(7 downto 0) );
end entity;

architecture Impl of bcd is
component BCD4adder is
port(BCDa, BCDb: in std_logic_vector(3 downto 0);
    BCDs: out std_logic_vector(3 downto 0);
    BCDcarry: out std_logic );
end component;

component BCD4suber is
port(Sa, Sb: in std_logic_vector(3 downto 0);
    Ss: out std_logic_vector(3 downto 0);
    Ssgn: out std_logic );
end component;

signal high, low, tmp1, tmp2:std_logic_vector(3 downto 0);
signal zero:std_logic;
signal tmpc1, tmpc2:std_logic;
begin
zero<='0';
ua: BCD4Adder port map
    (BCDa=>SAa, BCDb=>SAb, BCDs=>tmp1, BCDcarry=>tmpc1);
us: BCD4suber port map
	(Sa=>SAa, Sb=>SAb, Ss=>tmp2, Ssgn=>tmpc2); 
high(3)<=operator and tmpc2;
high(2)<=operator and tmpc2;
high(1)<=operator and tmpc2;
high(0)<=(not operator) and tmpc1;
low(3)<=(operator and tmp2(3))or((not operator)and tmp1(3));
low(2)<=(operator and tmp2(2))or((not operator)and tmp1(2));
low(1)<=(operator and tmp2(1))or((not operator)and tmp1(1));
low(0)<=(operator and tmp2(0))or((not operator)and tmp1(0));
sum(7 downto 4)<=high;
sum(3 downto 0)<=low;
end architecture Impl;