ivga.tan.rpt

用VHDL写的计算器

; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_vga         ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_vga'                                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                        ; To                               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 101.60 MHz ( period = 9.843 ns )                    ; VgaInterface:u2|vector_x[6] ; VgaInterface:u2|char_address[10] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 9.582 ns                ;
; N/A                                     ; 102.65 MHz ( period = 9.742 ns )                    ; VgaInterface:u2|vector_x[8] ; VgaInterface:u2|char_address[10] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 9.481 ns                ;
; N/A                                     ; 103.97 MHz ( period = 9.618 ns )                    ; VgaInterface:u2|vector_y[2] ; VgaInterface:u2|char_address[13] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 9.357 ns                ;
; N/A                                     ; 103.97 MHz ( period = 9.618 ns )                    ; VgaInterface:u2|vector_y[2] ; VgaInterface:u2|char_address[12] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 9.357 ns                ;
; N/A                                     ; 104.06 MHz ( period = 9.610 ns )                    ; VgaInterface:u2|vector_y[2] ; VgaInterface:u2|char_address[11] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 9.349 ns                ;
; N/A                                     ; 107.11 MHz ( period = 9.336 ns )                    ; VgaInterface:u2|vector_y[4] ; VgaInterface:u2|char_address[13] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 9.075 ns                ;
; N/A                                     ; 107.11 MHz ( period = 9.336 ns )                    ; VgaInterface:u2|vector_y[4] ; VgaInterface:u2|char_address[12] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 9.075 ns                ;
; N/A                                     ; 107.20 MHz ( period = 9.328 ns )                    ; VgaInterface:u2|vector_y[4] ; VgaInterface:u2|char_address[11] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 9.067 ns                ;
; N/A                                     ; 107.38 MHz ( period = 9.313 ns )                    ; VgaInterface:u2|vector_x[6] ; VgaInterface:u2|char_address[12] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 9.052 ns                ;
; N/A                                     ; 108.47 MHz ( period = 9.219 ns )                    ; VgaInterface:u2|vector_x[7] ; VgaInterface:u2|char_address[10] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.958 ns                ;
; N/A                                     ; 108.55 MHz ( period = 9.212 ns )                    ; VgaInterface:u2|vector_x[8] ; VgaInterface:u2|char_address[12] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.951 ns                ;
; N/A                                     ; 109.40 MHz ( period = 9.141 ns )                    ; VgaInterface:u2|vector_y[3] ; VgaInterface:u2|char_address[13] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.880 ns                ;
; N/A                                     ; 109.40 MHz ( period = 9.141 ns )                    ; VgaInterface:u2|vector_y[3] ; VgaInterface:u2|char_address[12] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.880 ns                ;
; N/A                                     ; 109.49 MHz ( period = 9.133 ns )                    ; VgaInterface:u2|vector_y[3] ; VgaInterface:u2|char_address[11] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.872 ns                ;
; N/A                                     ; 109.95 MHz ( period = 9.095 ns )                    ; VgaInterface:u2|vector_y[7] ; VgaInterface:u2|char_address[13] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.834 ns                ;
; N/A                                     ; 109.95 MHz ( period = 9.095 ns )                    ; VgaInterface:u2|vector_y[7] ; VgaInterface:u2|char_address[12] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.834 ns                ;
; N/A                                     ; 110.05 MHz ( period = 9.087 ns )                    ; VgaInterface:u2|vector_y[7] ; VgaInterface:u2|char_address[11] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.826 ns                ;
; N/A                                     ; 112.23 MHz ( period = 8.910 ns )                    ; VgaInterface:u2|vector_y[2] ; VgaInterface:u2|char_address[10] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.649 ns                ;
; N/A                                     ; 112.61 MHz ( period = 8.880 ns )                    ; VgaInterface:u2|vector_x[6] ; VgaInterface:u2|char_address[11] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.619 ns                ;
; N/A                                     ; 113.29 MHz ( period = 8.827 ns )                    ; VgaInterface:u2|vector_x[9] ; VgaInterface:u2|char_address[13] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.566 ns                ;
; N/A                                     ; 113.29 MHz ( period = 8.827 ns )                    ; VgaInterface:u2|vector_x[9] ; VgaInterface:u2|char_address[12] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.566 ns                ;
; N/A                                     ; 113.39 MHz ( period = 8.819 ns )                    ; VgaInterface:u2|vector_x[9] ; VgaInterface:u2|char_address[11] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.558 ns                ;
; N/A                                     ; 113.58 MHz ( period = 8.804 ns )                    ; VgaInterface:u2|vector_x[3] ; VgaInterface:u2|char_address[10] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.543 ns                ;
; N/A                                     ; 113.70 MHz ( period = 8.795 ns )                    ; VgaInterface:u2|vector_x[3] ; VgaInterface:u2|char_address[13] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.534 ns                ;
; N/A                                     ; 113.70 MHz ( period = 8.795 ns )                    ; VgaInterface:u2|vector_x[3] ; VgaInterface:u2|char_address[12] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.534 ns                ;
; N/A                                     ; 113.80 MHz ( period = 8.787 ns )                    ; VgaInterface:u2|vector_x[3] ; VgaInterface:u2|char_address[11] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.526 ns                ;
; N/A                                     ; 113.91 MHz ( period = 8.779 ns )                    ; VgaInterface:u2|vector_x[8] ; VgaInterface:u2|char_address[11] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.518 ns                ;
; N/A                                     ; 115.09 MHz ( period = 8.689 ns )                    ; VgaInterface:u2|vector_x[7] ; VgaInterface:u2|char_address[12] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.428 ns                ;
; N/A                                     ; 115.90 MHz ( period = 8.628 ns )                    ; VgaInterface:u2|vector_y[4] ; VgaInterface:u2|char_address[10] ; clk_vga    ; clk_vga  ; None                        ; None                      ; 8.367 ns                ;