test_gr.v

来自「本代码是在modelsim下运行的模拟8×8位的CPU」· Verilog 代码 · 共 47 行

module testbench_GR;
   wire [7:0] GR_out,GR_in;
   wire [2:0] GR_address;
   wire clk,reset,load_enable;

   GR g (GR_out,GR_in,clk,reset,GR_address,load_enable);
   test t (GR_out,GR_in,clk,reset,GR_address,load_enable);
endmodule

module test(GR_out,GR_in,clk,reset,GR_address,load_enable);
   parameter width=8;
    
   input [width-1:0] GR_out; //GR?????
   output [width-1:0] GR_in; //GR?????
   output clk;               //(??)????????
   output reset;             //(???????????
   output [2:0] GR_address;  //???????
   output load_enable;       //????
                      
   reg   [3:0] j;
   reg   [2:0] GR_address;
   reg   [width-1:0] GR_in;
   reg   clk,reset,load_enable;
   
   initial begin 
      $monitor($time,,,"GR_out=%b,GR_in=%b,clk=%b,reset=%b,GR_address=%b,load_enable=%b",
               GR_out,GR_in,clk,reset,GR_address,load_enable); //????
        
         #5 reset=0;
         #5 reset=1;
         
         #5 clk=0;
         #5 clk=1;GR_in=0;load_enable=0;GR_address=3'b000;
          
         #5 for(j=0;j<=7;j=j+1)
              begin
               #5 clk=0;
               #5 clk=1;GR_in=j;load_enable=1;GR_address=j;
            end 
         
         #5 reset=0;
         #100 $stop;
     end    
endmodule