kd_cpu.v

本代码是在modelsim下运行的模拟8×8位的CPU

module KD_CPU(data,address_out,RW,OE,CS,clk,reset);
    parameter width=8;
     
    inout  [width-1:0] data;//????
    output [7:0] address_out;   //??????
    output RW;                  //????
    output CS;		    //??
    output OE;		    //????
    
    input  clk;                 //??
    input  reset;               //????
    
    wire  [width-1:0] data_in; //????
    wire  [width-1:0] data_out; //????
    wire [width-1:0] data_bus;  //????
    wire [width-1:0] ALU_out;   //??ALU???????
    wire [width-1:0] GR_out;    //??????GR???????
    wire [7:0] IR_out;          //????????????????
    wire [7:0] AC_out;          //???????????
    wire is_zero;               //????????Z????????
    wire C_out;                 //C???????
    wire C_in;                  //C???????
    wire Z_out;                 //Z???????
   
    
    wire [7:0] AR_address;      //????????????
    wire [7:0] PC_address;      //??????PC??????
    wire [2:0] GR_address;      //?????????

    wire [4:0] ALU_OP;          //ALU??????
    wire [1:0] mux_C_sel;       //C??????????????
    wire [1:0] mux_DB_sel;      //????DB?????????
    wire mux_AB_sel;
    
    wire CLE;                   //C???????
    wire ZLE;                   //Z???????
    wire IRLE;                  //IR??
    wire ARLE;                  //AR??
    wire ACLE;                  //AC??
    wire GRLE;                  //???????
    wire PCLE;                  //PC????
    wire PCCE;                  //PC????
    wire ALU_C;                 //?ALU?????
    
    assign data_out=data_bus;   //???????                 
    assign data_in=data;   //???????
    assign data=((~CS) && (~RW) )? data_out:'bz;
    assign is_zero=(ALU_out == 'b0)?'b1:'b0;//?"0"??
    
    //clock clock (clk);
    
    register #(1) C  (.register_out(C_out),.register_in(C_in),.clk(clk),
                      .reset(reset),.load_enable(CLE)); //??C?????????
    register #(1) Z  (.register_out(Z_out),.register_in(is_zero),.clk(clk),
                      .reset(reset),.load_enable(ZLE)); //??Z????????
    register #(8) IR (.register_out(IR_out),.register_in(data_bus),.clk(clk),
                      .reset(reset),.load_enable(IRLE));//???????
    register #(8) AR (.register_out(AR_address),.register_in(data_bus),.clk(clk),
                      .reset(reset),.load_enable(ARLE));//???????                  
    register #(8) AC (.register_out(AC_out),.register_in(data_bus),.clk(clk),
                      .reset(reset),.load_enable(ACLE));//?????   
                                                                                                                                                                                      
    mux4 #(1) mux_C  (.mux4_out(C_in),.m0_in(ALU_C),.m1_in(AC_out[0]),.m2_in(AC_out[7]),
                      .m3_in(1'b0),.sel_in(mux_C_sel)); //??C????????   //CS????
    mux4 #(8) mux_DB (.mux4_out(data_bus),.m0_in(AC_out),.m1_in(ALU_out),
                      .m2_in(data_in),.m3_in(8'b0),.sel_in(mux_DB_sel));//???????????'b00??AC?'b01??ALU_O,'b10??????
    mux2 #(8) mux_AB (.mux2_out(address_out),.m0_in(PC_address),.m1_in(AR_address),
                      .sel_in(mux_AB_sel));//???????????'b0??PC?'b1??AR?
 
    GR  GR  (.GR_out(GR_out),.GR_in(data_bus),.clk(clk),.reset(reset),
             .GR_address(GR_address),.load_enable(GRLE));//????????

    ALU ALU (.ALU_O(ALU_out),.ALU_C(ALU_C),.C_in(C_out),.ALU_OP(ALU_OP),
             .AC_in(AC_out),.GR_in(GR_out));//??ALU

    PC  PC  (.pc_out(PC_address),.pc_in(data_bus),.clk(clk),.reset(reset),
             .load_enable(PCLE),.count_enable(PCCE));//???????
    
    CU  CU  (.CLE(CLE),.ZLE(ZLE),.ALU_OP(ALU_OP),.ACLE(ACLE),.GR_address(GR_address),
             .GRLE(GRLE),.IRLE(IRLE),.ARLE(ARLE),.PCLE(PCLE),.PCCE(PCCE),.mux_C_sel(mux_C_sel),
             .mux_DB_sel(mux_DB_sel),.mux_AB_sel(mux_AB_sel),.RW(RW),.CS(CS),.OE(OE),.clk(clk),
             .reset(reset),.C_in(C_out),.Z_in(Z_out),.IR_in(IR_out));//?????
endmodule