📄 mux2.v
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module mux2(mux2_out,m0_in,m1_in,sel_in);
parameter width=8;
output [width-1:0] mux2_out; //??????
input [width-1:0] m0_in; //??????0
input [width-1:0] m1_in; //??????1
input sel_in; //????
reg [width-1:0] mux2_out;//??????????????????
always @(m0_in or m1_in or sel_in)
begin
case(sel_in)
'b0:mux2_out = m0_in;
'b1:mux2_out = m1_in;
endcase
end
endmodule
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