testbench.v

本代码是在modelsim下运行的模拟8×8位的CPU

module testbench;
wire  [7:0] data,address_out;
   wire  CS;
   wire  RW;
   wire  OE;
   
   wire clk;
   reg reset;
   
   KD_CPU  b  (.data(data),.address_out(address_out),.CS(CS),.RW(RW),.OE(OE),.clk(clk),.reset(reset));
   memory  m  (.mem_data(data),.mem_address(address_out),.CS(CS),.RW(RW),.OE(OE)); 
   clock   c  (.clk(clk));
     
   initial
     begin
       $monitor($time,,,"AC=%h,AR=%d,AB_sel=%b,IR=%d,PC=%d,state=%d,mux_DB_sel=%b,mem[%d]=%h,GR[%d]=%h,ALU=%h,GR_address=%d,GR_out=%h,GR[1]=%h,GR[0]=%h,c=%b,Z=%b",
                b.AC.register_out,b.AR.register_out,b.mux_AB_sel,b.IR.register_out,b.PC.pc_out,b.CU.state,b.mux_DB_sel,
                b.AR.register_out,m.mem[127],b.IR.register_out[2:0],b.GR.GR_out,b.ALU.ALU_O,b.GR.GR_address,b.GR.GR_out,b.GR.register[1],b.GR.register[0],b.C.register_out,b.Z.register_out);             	


         m.mem[0] = 'h0; m.mem[4] = 'h10;m.mem[1]=4;//MOV Mi-->AC
   
        m.mem[2]='b00001000;m.mem[3]='d127; //MOV AC-->Mi
        
        m.mem[5]='b00011001; //MOV AC,Ri
        
        m.mem[6]='h0;m.mem[7]=119;m.mem[119]='h37; //MOV Mi-->AC
        
        m.mem[8]='b00100000;  //AC+Ri
        
        m.mem[9]='b00101000;  //AC-Ri
        
        m.mem[10]='b00110000;  //AC+Ri+C
        
        m.mem[11]='b00111000;  //AC-Ri-C
        
        m.mem[12]= 'b01000000; //AC&Ri/////???????????????????????
        
        m.mem[13]='b01001000;   //AC orx Ri
        
        m.mem[14]='b01010000;   //SHCL Ri,C
        
        m.mem[15]='b01011000;    //SHCR Ri,C
        
 //       m.mem[16]='b01100000;    //JMP Mi
 //       m.mem[17]=8;
  
 //       m.mem[16]='b01101000;   //JNZ Mi
 //       m.mem[17]=8;
 
 //       m.mem[16]='b01110000;    //JNZ Mi
 //       m.mem[17]=8;
        
        m.mem[16]='b01111000;    //HTL
        m.mem[17]=8;
        
        
	reset = 0;
	#6 reset=1;
           		
           	
  	#1000 $stop;
   end

endmodule