test_pc.v

来自「本代码是在modelsim下运行的模拟8×8位的CPU」· Verilog 代码 · 共 54 行

module testbench_pc;
   wire clk,reset,load_enable,count_enable;
   wire [7:0] pc_out,pc_in;
   
   PC p (pc_out,pc_in,clk,reset,load_enable,count_enable);
   test t (pc_out,pc_in,clk,reset,load_enable,count_enable);
endmodule
   
module test(pc_out,pc_in,clk,reset,load_enable,count_enable);
   parameter    width=8;

   input[width-1:0] pc_out;    //PC??????
   output [width-1:0] pc_in;   //PC??????
   output clk;                 //????????
   output reset;               //????????
   output load_enable;         //????
   output count_enable;        //????
   reg   [width-1:0] pc_in;
   reg clk,reset,load_enable,count_enable; 
   
   initial begin
      $monitor($time,,,"pc_out=%b,pc_in=%b,clk=%b,reset=%b,load_enable=%b,count_enable=%b",pc_out,pc_in,clk,reset,load_enable,count_enable);
      
      #5 reset=0;pc_in=8'b00000111;
      #5 reset=1;pc_in=8'b00100101;
      #5 clk=1;
      #5 clk=0; 
      #5 clk=1;
      #5 clk=0;
      #5 clk=1;
         load_enable=1;
      #5 clk=0;
      #5 clk=1 ;
         load_enable=1;count_enable=1;
      #5 reset=0;
      #5 clk=0;
      #5 clk=1;
         count_enable=1;
      #5 reset=1;
      #5 reset=0;
      #5 reset=1;
         count_enable=1;
         load_enable=0;
      #5 clk=0;
      #5 clk=1;
         count_enable=0;
         load_enable=1;
      #5 clk=0;
      #5 clk=1;
         load_enable=0;count_enable=1;
   end
endmodule