mux4.v

来自「本代码是在modelsim下运行的模拟8×8位的CPU」· Verilog 代码 · 共 24 行

module mux4(mux4_out,m0_in,m1_in,m2_in,m3_in,sel_in);
   parameter width = 8;
     
   output[width-1:0] mux4_out;//??????
   input [width-1:0] m0_in;   //??????0?sel_in=`b00
   input [width-1:0] m1_in;   //??????1?sel_in='b01
   input [width-1:0] m2_in;   //??????2?sel_in='b10
   input [width-1:0] m3_in;   //??????3?sel_in='b11
   input [1:0]       sel_in;  //??????
   
   reg   [width-1:0] mux4_out;//???????????????????????zzzzzzzzzzzzzzzzzzzzzzz

   always @(m0_in or m1_in or m2_in or m3_in or sel_in)
      begin
	case(sel_in)
	'b00:mux4_out = m0_in;
	'b01:mux4_out = m1_in;
	'b10:mux4_out = m2_in;
	'b11:mux4_out = m3_in;
	endcase
      end
endmodule