test_cheng.v

本代码是在modelsim下运行的模拟8×8位的CPU

module testbench_cheng;
wire  [7:0] data,address_out;
   wire  CS;
   wire  RW;
   wire  OE;
   
   wire clk;
   reg reset;
   
   KD_CPU  b  (.data(data),.address_out(address_out),.CS(CS),.RW(RW),.OE(OE),.clk(clk),.reset(reset));
   memory  m  (.mem_data(data),.mem_address(address_out),.CS(CS),.RW(RW),.OE(OE)); 
   clock   c  (.clk(clk));
     
   initial
     begin
      // $monitor($time,,,"AC=%h,AR=%d,AB_sel=%b,IR=%d,PC=%d,state=%d,mux_DB_sel=%b,mem[%d]=%h,GR[%d]=%h,ALU=%h,GR_address=%d,GR_out=%h,GR[1]=%h,GR[0]=%h,c=%b,Z=%b",
       //         b.AC.register_out,b.AR.register_out,b.mux_AB_sel,b.IR.register_out,b.PC.pc_out,b.CU.state,b.mux_DB_sel,
        //        b.AR.register_out,m.mem[127],b.IR.register_out[2:0],b.GR.GR_out,b.ALU.ALU_O,b.GR.GR_address,b.GR.GR_out,b.GR.register[1],b.GR.register[0],b.C.register_out,b.Z.register_out);             	
	 $monitor($time,	 "   AC=%d,	 AR=%d,	 AB_sel=%d,	 IR=%b,	 PC=%d,	 state=%d,	  mux_DB_sel=%d,	  ALU_O=%d,   ALU_C=%d	  GR_address=%d,	 GR_out=%d,	 c=%d,	 Z=%d,GR[5]=%b, GR[6]=%b; data=%b",
                b.AC.register_out,b.AR.register_out,b.mux_AB_sel,b.IR.register_out,b.PC.pc_out,b.CU.state,b.mux_DB_sel,
                b.ALU.ALU_O,b.ALU.ALU_C,b.GR.GR_address,b.GR.GR_out,b.C.register_out,b.Z.register_out,b.GR.register[5],b.GR.register[6],data);             	

	m.mem[0]='b00000000	;	
	m.mem[52]='b00000001	;	
	m.mem[1]='b00110100	;//MOV AC MEM
	m.mem[2]='b00010000	;	//MOV GR[0] AC	?????
	m.mem[3]='b00000000;	
	m.mem[4]='b00110011;
	m.mem[51]='b01000101;		//MOV AC MEM----------------------------????????--??
	m.mem[5]='b00010010;	//MOV GR[2] AC   ????
	m.mem[6]='b00000000;
	m.mem[7]='b00110010;
	m.mem[50]='b00100001;		//MOV AC MEM-------------------????????--???
m.mem[8]='b00010001		;	//MOV GR[1] AC   ?????? ????
m.mem[9]='b00010011		;	//MOV GR[3] AC   ?????? ????
m.mem[10]='b00000000;
m.mem[11]='b00110001;
m.mem[49]='b10000000;
m.mem[12]='b00010100;			//GR[4]
m.mem[13]='b00011000		;	
m.mem[14]='b01000010		;	//??????????0
m.mem[15]='b01101000		;	
m.mem[16]='b00010011		;	//?????19?????
m.mem[17]='b00011011		;	
m.mem[18]='b00010101		;	//???????
m.mem[19]='b00011000		;	//????????	-----		19
m.mem[20]='b01000000;
m.mem[21]='b01101000;
m.mem[22]='b00110000;		//??
m.mem[23]='b01010001	;		
m.mem[24]='b00010001;
m.mem[25]='b01011011;
m.mem[26]='b00010011	;		//??
m.mem[27]='b01011000;
m.mem[28]='b00010000;
m.mem[29]='b01000010;
m.mem[30]='b01101000;
m.mem[31]='b00100011;//?????			?????
m.mem[32]='b00011011;
m.mem[33]='b00100101;
m.mem[34]='b00010101; 
m.mem[35]='b00011100;		//????????
m.mem[36]='b00010111;
m.mem[37]='b01010100;
m.mem[38]='b00010100;
m.mem[39]='b00011111;
m.mem[40]='b01000010;
m.mem[41]='b01101000;
m.mem[42]='b00010011;
m.mem[43]='b00011001;		
m.mem[44]='b00110110;					//??????
m.mem[45]='b00010110;					
m.mem[46]='b01100000;
m.mem[47]='b00010011;

m.mem[48]='b01111000;		//40???








	reset = 0;
	#6 reset=1;
           		
           	
  	#10000 $stop;
   end

endmodule