gr.v

本代码是在modelsim下运行的模拟8×8位的CPU

module GR(GR_in,GR_out,load_enable,GR_address,reset,clk);
 output [7:0]GR_out;
 input	[7:0]GR_in;
 input	load_enable;                     //?????    					
 input	reset;                           //?????
 input	clk;
 input	[2:0]GR_address;
 
 
 
 reg   [7:0] GR_out;
 reg   [7:0] register[7:0];
 
 integer i;
 always @(posedge clk or negedge reset )
 begin
     if(!reset)
     begin
         for( i=0;i<=7;i=i+1) 
         register[i]<='b0;
     end
     else if(load_enable ) 
     begin
     	 case(GR_address)	   
      	 'b000:register[0]<=GR_in;
      	 'b001:register[1]<=GR_in;
      	 'b010:register[2]<=GR_in;
      	 'b011:register[3]<=GR_in;
      	 'b100:register[4]<=GR_in;
      	 'b101:register[5]<=GR_in;
      	 'b110:register[6]<=GR_in;
      	 'b111:register[7]<=GR_in;
      	 endcase
      end
  end
  
      
  always @(GR_address or register[0] or register[1] or register[2] or register[3] or register[4] or register[5] or register[6] or register[7])//????
       begin
	 case(GR_address)
	   'b000:GR_out=register[0];
	   'b001:GR_out=register[1];
	   'b010:GR_out=register[2];
	   'b011:GR_out=register[3];
	   'b100:GR_out=register[4];
	   'b101:GR_out=register[5];
	   'b110:GR_out=register[6];
	   'b111:GR_out=register[7];
	endcase
       end
       
 endmodule