test_mem.v

本代码是在modelsim下运行的模拟8×8位的CPU

module testbench_mem;
   wire [7:0] mem_data,address_in;
   wire CS,RW,OE; 
   
   test t (mem_data,address_in,CS,RW,OE);
   memory m (mem_data,address_in,CS,RW,OE);
endmodule
   
module test(mem_data,address_in,CS,RW,OE);
   parameter width=8;
   
   inout[width-1:0] mem_data;	//??????
   output [7:0] address_in;	//??????
   output CS,RW,OE;	//????
   
   wire[width-1:0] mem_out;
          
   reg  [width-1:0] mem_in;
   reg   [7:0] address_in;
   reg   CS,RW,OE;
   
// ????????CS?RW????
   assign mem_out = mem_data;
   assign mem_data =(~CS & ~ RW) ? mem_in : 'bz;
   
   initial begin
      $monitor($time,,,"mem_out=%d,\t mem_in=%d,\t address_in=%d,\t CS=%b,RW=%b,RD=%b",
               mem_out,mem_in,address_in,CS,RW,OE);//????
      CS = 1;
      RW = 1;
      OE = 1;  

// RWite data
      #5 mem_in=0;address_in=0;CS=0;RW=0;
      #5 mem_in=1;address_in=1;CS=0;RW=0;
      #5 mem_in=255;address_in=255;CS=0;RW=0;

// read data
      #5 address_in=0;CS=0;RW=1;OE=0;
      #5 address_in=1;CS=0;RW=1;OE=0;
      #5 address_in=255;CS=0;RW=1;OE=0;
      #5 address_in=255;CS=0;RW=1;OE=0;

      #5 $stop;
    end
endmodule

 //                 0  mem_out=  z,	 mem_in=  x,	 address_in=  x,	 CS=1,RW=1,RD=1

      //            5  mem_out=  0,	 mem_in=  0,	 address_in=  0,	 CS=0,RW=0,RD=1
       //          10  mem_out=  1,	 mem_in=  1,	 address_in=  1,	 CS=0,RW=0,RD=1
        //          15  mem_out=255,	 mem_in=255,	 address_in=255,	 CS=0,RW=0,RD=1
         //         20  mem_out=  0,	 mem_in=255,	 address_in=  0,	 CS=0,RW=1,RD=0
        //        25  mem_out=  1,	 mem_in=255,	 address_in=  1,	 CS=0,RW=1,RD=0
         //       30  mem_out=255,	 mem_in=255,	 address_in=255,	 CS=0,RW=1,RD=0