test_clock.v

本代码是在modelsim下运行的模拟8×8位的CPU

module testbench_clock;
   wire clk;
   clock c (clk);
   test t (clk);
endmodule

module test(clk);
   input clk;
   initial begin
     $monitor($time,,,"clock=%b",clk);
     #50 $stop;
   end
endmodule