cu.v

本代码是在modelsim下运行的模拟8×8位的CPU

module CU (CLE,ZLE,ALU_OP,ACLE,GR_address,GRLE,IRLE,ARLE,PCLE,PCCE,
           mux_C_sel,mux_DB_sel,mux_AB_sel,RW,OE,CS,clk,reset,C_in,Z_in,IR_in);
   
   parameter FIRST = 'b00,SECOND = 'b01,THIRD = 'b10,HLT = 'b11;       
    
   // ??????      
   output CLE;    reg CLE;         // CLE?1b?C??????????
   output ZLE;    reg ZLE;         // ZLE?1b?Z?????????
   output ACLE;   reg ACLE;        // ACLE?1b????AC?????
   output GRLE;   reg GRLE;        // GRLE?1b??????GR?????
   output ARLE;   reg ARLE;        // ARLE?1b??????AR?????
   output IRLE;   reg IRLE;        // IRLE?1b??????IR????
   output PCLE;   reg PCLE;        // PCLE?1b??????PC????
   output PCCE;   reg PCCE;        // PCCE?1b???????????

   output [3:0] ALU_OP;      reg [4:0] ALU_OP;      //ALU_OP: 5b?????????ALU??????
   output [2:0] GR_address;  reg [2:0] GR_address;  //GR_address?3b??????GR???
   output [1:0] mux_C_sel;   reg [1:0] mux_C_sel;   //mux_C_sel?2????C?????????????
   output [1:0] mux_DB_sel;  reg [1:0] mux_DB_sel;  //mux_DB_sel?2????????DB????????
   output mux_AB_sel;        reg mux_AB_sel;        //mux_AB_sel?1????????AB????????
   output RW;                reg RW;                //RW????????
   output OE;			  reg OE;
   output CS;                reg CS;
   
   // ??????  
   input  clk;              //????????
   input  reset;            //??????????
   input  C_in;             //?????????
   input  Z_in;             //????????
   input  [7:0]  IR_in;     //IR_in?8b???????????
      
   reg [1:0] state; //????

   always @(posedge clk or negedge reset) //??????
       begin
          if(!reset) //?????????????
                state <=FIRST; 
          else begin
                case(state)
                FIRST:state <= SECOND; //FIST-->SECOND
                SECOND:state <=THIRD;  //SECOD-->THIRD
                THIRD:if (IR_in[7:3] == 'b01111) // HTL???????????????????????????????????
                                state <= HLT;
                      else
                                state <=FIRST;    //THIRD-->FIRST
                HLT:state <= HLT;      //????????
                endcase
          end
       end

   always @(state or C_in or Z_in or IR_in) //????????
      begin
      //???????????0?
        CLE = 'b0;    
        ZLE = 'b0;
        ALU_OP = 'b0;
        ACLE = 'b0;
        GR_address = 'b0;
        GRLE = 'b0;
        IRLE = 'b0;
        ARLE = 'b0;
        PCLE = 'b0;
        PCCE = 'b0;
        mux_C_sel = 2'b00;
        mux_DB_sel = 2'b00;
        mux_AB_sel = 'b0;
        RW = 'b1;
	 OE = 'b1;
        CS = 'b1;
     //??????????state??????IR???????????????
        case(state) 
        FIRST:begin  //?????              
                mux_AB_sel = 'b0;  //??????PC  ?????????????????????????????????????????????????????????            
                mux_DB_sel = 'b10; //?????????????
		  OE= 'b0;
		  CS= 'b0;
                IRLE = 'b1;        //???????
                PCCE = 'b1;        //PC????
        end
        SECOND:begin //???????
                case(IR_in[7:3])
                
                //????? ?L/S??
                'b00000: //MOV Mi-->AC
                     begin                               
                       	mux_AB_sel = 'b0;  //??????PC ?????????????????????????????????????????????????????
                       	mux_DB_sel = 'b10; //???????????? 
			OE= 'b0;
			  CS= 'b0;
                       	PCCE = 'b1;        //PC????
                       	ARLE = 'b1;        //???????
  		     end
               'b00001://MOV AC-->Mi
		     begin 
			mux_AB_sel = 'b0;  //??????PC???   ?????  1-?0
			mux_DB_sel = 'b10; //??????????
			OE= 'b0;
			  CS= 'b0;
			PCCE = 'b1;	     //PC?????
			ARLE = 'b1;	     //???????
                     end  
                                
                //???????ALU???????????????
                //??????  
                'b00010:begin  //AC-->GR
                           GR_address = IR_in[2:0];  //GR?????????????
                           ALU_OP = IR_in[7:3];      //ALU?????
                           mux_DB_sel = 'b01;        //??????ALU_O
                           //GR_address = IR_in[2:0];  //GR?????????????
                           GRLE = 'b1;               //GR????
                           CLE= 'b1;
			   ZLE= 'b1;
			   mux_C_sel = 'b00;
                        end
                 //????AC???       
                'b00011: //GR-->AC
		        begin
		           GR_address =IR_in[2:0];
			   ALU_OP = IR_in[7:3];
			   mux_DB_sel = 'b01;   //??????ALU_0???
			   ACLE = 'b1;  
			   CLE= 'b1;
			   ZLE= 'b1;  
			   mux_C_sel = 'b00;            
			end
		 'b00100,
		 'b00101,
		 'b01000,
		 'b01001: //AC+Ri->AC
			begin
			   GR_address = IR_in[2:0];
		           ALU_OP = IR_in[7:3];
			   mux_DB_sel = 'b01;     //????ALU-O????
			   ACLE= 'b1;
			   CLE= 'b1;
			   ZLE= 'b1;
			   mux_C_sel = 'b00;
			end
		 'b00110,
		 'b00111: //AC+Ri+C->AC
			begin
			   GR_address = IR_in[2:0];
			   ALU_OP = IR_in[7:3];
			   mux_DB_sel = 'b01;     //????ALU-O????
			   ACLE= 'b1;
			   CLE= 'b1;
			   ZLE= 'b1;
			   mux_C_sel = 'b00;
			end			
				
                'b01011,
		'b01010: //SHCL AC,GR
                       begin 
                           GR_address = IR_in[2:0];  //GR?????????????  
                           ALU_OP = IR_in[7:3];      //ALU?????
                           mux_DB_sel = 'b01;        //??????ALU_O
                           ACLE = 'b1;               //?????               //C???????
                           ZLE  = 'b1;               //Z???????
                            
                           if(IR_in[7:3]=='b01010)   //SHCR AC,GR
                              mux_C_sel = 'b01;      //C?????????AC_out[0]?????????????????????????
                           if(IR_in[7:3]=='b01011)   //SHCL AC,GR
                              mux_C_sel = 'b10;      //C?????????AC_out[7]
                       end 
                    
                //????? ????? 
                'b01100,
                'b01101,  
                'b01110: //JC Mi
                     begin
                        mux_AB_sel = 'b0;  //??????PC???????????????????????????
                        mux_DB_sel = 'b10; //?????????????
                        CS= 'b0;
			OE= 'b0;
                        case (IR_in[4:3])
                        'b00:PCLE = 'b1;   //PC???????????????
                        'b01:begin 
                        				if (Z_in)
			 	    PCLE = 'b1; //??????0??
				else
				    PCCE = 'b1;
				end 

                        'b10:begin 
                        				if (!C_in)
			 	    PCLE = 'b1; //????????0??
				else
				    PCCE = 'b1;
				end  //???????0???????
                        endcase
			    
                     end
                 endcase
              end
                        
       THIRD:begin //????L/S???
                if(IR_in[7:3] == 'b00000||IR_in[7:3] == 'b00001) begin
                     mux_AB_sel = 'b1;     //??????AR????
                     if(!IR_in[3])
                       begin
                        mux_DB_sel = 'b10; //?????????????
                        ACLE = 'b1;        //AC??
			   OE = 'b0;
			   CS= 'b0;
                       end
                     else begin
                        mux_DB_sel = 'b00; //??????AC????
                        RW = 'b0;
			   CS= 'b0;
                     end
                end
             end
       endcase
   end
endmodule