test_mux2.v

来自「本代码是在modelsim下运行的模拟8×8位的CPU」· Verilog 代码 · 共 31 行

module testbench_mux2;
   wire [7:0] mux2_out,m0_in,m1_in;
   wire sel_in;
   
   test_mux2 t  (mux2_out,m0_in,m1_in,sel_in);
   mux2 m (mux2_out,m0_in,m1_in,sel_in);
endmodule

module test_mux2(mux2_out,m0_in,m1_in,sel_in);
   parameter width=8;
   
   input   [width-1:0] mux2_out;   //??????
   output  [width-1:0] m0_in;      //??????0
   output  [width-1:0] m1_in;      //??????1
   output  sel_in;                 //????

   reg     [width-1:0]  m0_in,m1_in;
   reg sel_in;
     
   initial begin
      $monitor($time,,,"mux2_out=%b,m0_in=%b,m1_in=%b,sel_in=%b",
               mux2_out,m0_in,m1_in,sel_in); //????
      
      #5 m0_in=1;m1_in=0;
      #5 m0_in=1;m1_in=0;sel_in=0;
      #5 m0_in=1;m1_in=0;sel_in=1;
   end   
endmodule