mem.v

来自「本代码是在modelsim下运行的模拟8×8位的CPU」· Verilog 代码 · 共 27 行

module memory(mem_data,mem_address,CS,RW,OE);
   parameter width=8;
   
   inout [width-1:0] mem_data;
   input [7:0] mem_address;  //??????
   input CS,RW,OE;           //????
             
   reg   [width-1:0] mem_out;
   wire   [width-1:0] mem_in;
   reg   [width-1:0] mem[255:0];
   
   assign mem_in=mem_data;
   assign mem_data=((~CS) && (~OE))? mem_out: 'bz;

   always @(mem_in or mem_address or CS or RW or OE)
      begin
	if(!CS)
	begin
	   if(!RW)  
	        mem[mem_address] = mem_in; //???
	   else
	   if(!OE)
           	mem_out = mem[mem_address];//???
        end
      end
 endmodule