alu.v

本代码是在modelsim下运行的模拟8×8位的CPU

module ALU(ALU_O,ALU_C,C_in,ALU_OP,AC_in,GR_in);

  parameter width=8;

  output ALU_C;               //??ALU??????????
  output [width-1:0] ALU_O;   //??ALU??????????
  input  C_in;                //??C??????????
  input  [4:0] ALU_OP;            //???
  input  [width-1:0] AC_in;   //???????AC???
  input  [width-1:0] GR_in;   //???????GR???
  reg    [width-1:0] ALU_O;
  reg    ALU_C;

  always @(C_in or ALU_OP or AC_in or GR_in)
         begin
	    case (ALU_OP)
	      5'b00010:begin {ALU_C,ALU_O}={C_in,AC_in};end       //??AC?????  {}  ?????
      	      5'b00011:begin {ALU_C,ALU_O}={C_in,GR_in};end       //??GR?????
              5'b00100:begin {ALU_C,ALU_O}=AC_in+GR_in;end        //??
	      5'b00101:begin {ALU_C,ALU_O}=AC_in-GR_in;end        //??
	      5'b00110:begin {ALU_C,ALU_O}=AC_in+GR_in+C_in;end   //?????
	      5'b00111:begin {ALU_C,ALU_O}=AC_in-GR_in-C_in;end   //?????
	      5'b01000:begin {ALU_C,ALU_O}={C_in,AC_in&GR_in};end //????????
              5'b01001:begin {ALU_C,ALU_O}={C_in,AC_in^GR_in};end //?????????
	      5'b01010:begin {ALU_O,ALU_C}={1'b0,GR_in[7:1],1'b0};end       //????????????
	      5'b01011:begin {ALU_C,ALU_O}={1'b0,GR_in[6:0],1'b0};end       //????????????
	      default:begin  {ALU_C,ALU_O}={C_in,8'b0};end        //?????????????0?????
	    endcase
         end            
endmodule