__projnav.log

数字计时器

Phase 3: 158 unrouted;       REAL time: 1 mins 

Phase 4: 0 unrouted;       REAL time: 1 mins 2 secs 

Total REAL time to Router completion: 1 mins 2 secs 
Total CPU time to Router completion: 1 mins 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   13   |  0.061     |  0.489      |
+----------------------------+----------+--------+------------+-------------+
|            second          |Low-Skew  |    2   |  0.097     |  4.303      |
+----------------------------+----------+--------+------------+-------------+
|            minute          |   Local  |    2   |  0.000     |  3.444      |
+----------------------------+----------+--------+------------+-------------+
|          minute10          |   Local  |    2   |  0.000     |  3.443      |
+----------------------------+----------+--------+------------+-------------+
|              hour          |   Local  |    2   |  0.042     |  3.585      |
+----------------------------+----------+--------+------------+-------------+
|            _n0023          |   Local  |    1   |  0.000     |  0.648      |
+----------------------------+----------+--------+------------+-------------+
|         msecond10          |   Local  |    2   |  0.000     |  3.534      |
+----------------------------+----------+--------+------------+-------------+
|            _n0024          |   Local  |    1   |  0.000     |  0.796      |
+----------------------------+----------+--------+------------+-------------+
|         count<18>          |   Local  |    4   |  0.000     |  3.303      |
+----------------------------+----------+--------+------------+-------------+
|          second10          |   Local  |    2   |  0.000     |  3.505      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 mins 4 secs 
Total CPU time to PAR completion: 1 mins 2 secs 

Peak Memory Usage:  72 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file seg.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Jul 02 21:40:54 2002
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module seg . . .
PAR command line: par -w -intstyle ise -ol std -t 1 seg_map.ncd seg.ncd seg.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/doc/file/seg/SEG.vhd in Library work.
Entity <seg> (Architecture <behavioral>) compiled.
Entity <count10> (Architecture <behavioral>) compiled.
Entity <count6> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <seg> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 347: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 347: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 347: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1561 - G:/doc/file/seg/SEG.vhd line 296: Mux is complete : default of case is discarded
WARNING:Xst:819 - G:/doc/file/seg/SEG.vhd line 270: The following signals are missing in the process sensitivity list:
   MsecSeg1, MsecSeg2, SecSeg1, SecSeg2, MinSeg1, HourSeg1.
Entity <seg> analyzed. Unit <seg> generated.

Analyzing Entity <count10> (Architecture <behavioral>).
Entity <count10> analyzed. Unit <count10> generated.

Analyzing Entity <count6> (Architecture <behavioral>).
Entity <count6> analyzed. Unit <count6> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <count6>.
    Related source file is G:/doc/file/seg/SEG.vhd.
    Found 3-bit up counter for signal <q>.
    Summary:
	inferred   1 Counter(s).
Unit <count6> synthesized.


Synthesizing Unit <count10>.
    Related source file is G:/doc/file/seg/SEG.vhd.
    Found 4-bit up counter for signal <q>.
    Summary:
	inferred   1 Counter(s).
Unit <count10> synthesized.


Synthesizing Unit <seg>.
    Related source file is G:/doc/file/seg/SEG.vhd.
WARNING:Xst:646 - Signal <MinSeg2> is assigned but never used.
WARNING:Xst:646 - Signal <HourSeg2> is assigned but never used.
    Found 16x8-bit ROM for signal <SecSeg1>.
    Found 16x4-bit ROM for signal <$n0021>.
    Found 16x4-bit ROM for signal <$n0022>.
    Found 16x8-bit ROM for signal <MsecSeg1>.
    Found 16x8-bit ROM for signal <MsecSeg2>.
WARNING:Xst:737 - Found 1-bit latch for signal <MinSeg1_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <HourSeg1_0>.
    Found 1-of-8 decoder for signal <seg_sel>.
    Found 19-bit up counter for signal <count>.
    Summary:
	inferred   5 ROM(s).
	inferred   1 Counter(s).
	inferred   1 Decoder(s).
Unit <seg> synthesized.

WARNING:Xst:524 - All outputs of the instance <u6> of the block <count6> are unconnected in block <seg>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 5
 16x8-bit ROM                      : 3
 16x4-bit ROM                      : 2
# Counters                         : 8
 19-bit up counter                 : 1
 4-bit up counter                  : 5
 3-bit up counter                  : 2
# Latches                          : 2
 1-bit latch                       : 2
# Decoders                         : 1
 1-of-8 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg> ...
Loading device for application Xst from file '2s300e.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg, actual ratio is 2.
FlipFlop count_9 has been replicated 1 time(s)
FlipFlop count_11 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300efg456-6 

 Number of Slices:                      82  out of   3072     2%  
 Number of Slice Flip Flops:            49  out of   6144     0%  
 Number of 4 input LUTs:               145  out of   6144     2%  
 Number of bonded IOBs:                 19  out of    329     5%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
second(_n00081:O)                  | NONE(*)(u1_q_0)        | 4     |
_n0024(_n00241:O)                  | NONE(*)(HourSeg1_0)    | 1     |
_n0023(_n00231:O)                  | NONE(*)(MinSeg1_0)     | 1     |
hour(_n00051:O)                    | NONE(*)(u5_q_3)        | 4     |
minute(_n00031:O)                  | NONE(*)(u3_q_2)        | 4     |
count_18:Q                         | NONE                   | 4     |
clk                                | BUFGP                  | 21    |
msecond10(_n00071:O)               | NONE(*)(u8_q_0)        | 4     |
minute10(_n00041:O)                | NONE(*)(u4_q_0)        | 3     |
second10(_n00021:O)                | NONE(*)(u2_q_0)        | 3     |
-----------------------------------+------------------------+-------+
(*) These 8 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.473ns (Maximum Frequency: 105.563MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 13.486ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\doc\file\seg/_ngo -uc seg.ucf -p
xc2s300e-fg456-6 seg.ngc seg.ngd 

Reading NGO file "G:/doc/file/seg/seg.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "seg.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39800 kilobytes

Writing NGD file "seg.ngd" ...

Writing NGDBUILD log file "seg.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s300efg456-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    8
Logic Utilization:
  Total Number Slice Registers:      49 out of  6,1