__projnav.log

数字计时器

INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 347: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 347: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1561 - G:/doc/file/seg/SEG.vhd line 296: Mux is complete : default of case is discarded
WARNING:Xst:819 - G:/doc/file/seg/SEG.vhd line 270: The following signals are missing in the process sensitivity list:
   MsecSeg1, MsecSeg2, SecSeg1, SecSeg2, MinSeg1, HourSeg1.
Entity <seg> analyzed. Unit <seg> generated.

Analyzing Entity <count10> (Architecture <behavioral>).
Entity <count10> analyzed. Unit <count10> generated.

Analyzing Entity <count6> (Architecture <behavioral>).
Entity <count6> analyzed. Unit <count6> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <count6>.
    Related source file is G:/doc/file/seg/SEG.vhd.
    Found 3-bit up counter for signal <q>.
    Summary:
	inferred   1 Counter(s).
Unit <count6> synthesized.


Synthesizing Unit <count10>.
    Related source file is G:/doc/file/seg/SEG.vhd.
    Found 4-bit up counter for signal <q>.
    Summary:
	inferred   1 Counter(s).
Unit <count10> synthesized.


Synthesizing Unit <seg>.
    Related source file is G:/doc/file/seg/SEG.vhd.
WARNING:Xst:646 - Signal <MinSeg2> is assigned but never used.
WARNING:Xst:646 - Signal <HourSeg2> is assigned but never used.
    Found 16x8-bit ROM for signal <SecSeg1>.
    Found 16x4-bit ROM for signal <$n0021>.
    Found 16x4-bit ROM for signal <$n0022>.
    Found 16x8-bit ROM for signal <MsecSeg1>.
    Found 16x8-bit ROM for signal <MsecSeg2>.
WARNING:Xst:737 - Found 1-bit latch for signal <MinSeg1_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <HourSeg1_0>.
    Found 1-of-8 decoder for signal <seg_sel>.
    Found 19-bit up counter for signal <count>.
    Summary:
	inferred   5 ROM(s).
	inferred   1 Counter(s).
	inferred   1 Decoder(s).
Unit <seg> synthesized.

WARNING:Xst:524 - All outputs of the instance <u6> of the block <count6> are unconnected in block <seg>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 5
 16x8-bit ROM                      : 3
 16x4-bit ROM                      : 2
# Counters                         : 8
 19-bit up counter                 : 1
 4-bit up counter                  : 5
 3-bit up counter                  : 2
# Latches                          : 2
 1-bit latch                       : 2
# Decoders                         : 1
 1-of-8 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg> ...
Loading device for application Xst from file '2s300e.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg, actual ratio is 2.
FlipFlop count_11 has been replicated 1 time(s)
FlipFlop count_13 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300efg456-6 

 Number of Slices:                      82  out of   3072     2%  
 Number of Slice Flip Flops:            49  out of   6144     0%  
 Number of 4 input LUTs:               145  out of   6144     2%  
 Number of bonded IOBs:                 19  out of    329     5%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
second(_n00081:O)                  | NONE(*)(u1_q_0)        | 4     |
_n0024(_n00241:O)                  | NONE(*)(HourSeg1_0)    | 1     |
_n0023(_n00231:O)                  | NONE(*)(MinSeg1_0)     | 1     |
hour(_n00051:O)                    | NONE(*)(u5_q_3)        | 4     |
minute(_n00031:O)                  | NONE(*)(u3_q_2)        | 4     |
count_18:Q                         | NONE                   | 4     |
clk                                | BUFGP                  | 21    |
msecond10(_n00071:O)               | NONE(*)(u8_q_0)        | 4     |
minute10(_n00041:O)                | NONE(*)(u4_q_0)        | 3     |
second10(_n00021:O)                | NONE(*)(u2_q_0)        | 3     |
-----------------------------------+------------------------+-------+
(*) These 8 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.473ns (Maximum Frequency: 105.563MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 13.486ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\doc\file\seg/_ngo -uc seg.ucf -p
xc2s300e-fg456-6 seg.ngc seg.ngd 

Reading NGO file "G:/doc/file/seg/seg.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "seg.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39800 kilobytes

Writing NGD file "seg.ngd" ...

Writing NGDBUILD log file "seg.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s300efg456-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    8
Logic Utilization:
  Total Number Slice Registers:      49 out of  6,144    1%
    Number used as Flip Flops:                     47
    Number used as Latches:                         2
  Number of 4 input LUTs:           110 out of  6,144    1%
Logic Distribution:
    Number of occupied Slices:                          79 out of  3,072    2%
    Number of Slices containing only related logic:     79 out of     79  100%
    Number of Slices containing unrelated logic:         0 out of     79    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          143 out of  6,144    2%
      Number used as logic:                       110
      Number used as a route-thru:                 33
   Number of bonded IOBs:            19 out of    325    5%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  1,271
Additional JTAG gate count for IOBs:  960
Peak Memory Usage:  68 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "seg_map.mrp" for details.
Completed process "Map".

Mapping Module seg . . .
MAP command line:
map -intstyle ise -p xc2s300e-fg456-6 -cm area -pr b -k 4 -c 100 -tx off -o seg_map.ncd seg.ngd seg.pcf
Mapping Module seg: DONE



Started process "Place & Route".





Constraints file: seg.pcf

Loading device database for application Par from file "seg_map.ncd".
   "seg" is an NCD, version 2.38, device xc2s300e, package fg456, speed -6
Loading device for application Par from file '2s300e.nph' in environment
D:/Xilinx.
Device speed data version:  PRODUCTION 1.17 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            19 out of 325     5%
      Number of LOCed External IOBs   19 out of 19    100%

   Number of SLICEs                   79 out of 3072    2%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989883) REAL time: 3 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
...
Phase 5.8 (Checksum:9bf97d) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs 

Writing design to file seg.ncd.

Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 3 secs 


Phase 1: 528 unrouted;       REAL time: 5 secs 

Phase 2: 496 unrouted;       REAL time: 59 secs