__projnav.log

数字计时器

=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
second(_n00081:O)                  | NONE(*)(u1_q_0)        | 4     |
_n0024(_n00241:O)                  | NONE(*)(HourSeg1_0)    | 1     |
_n0023(_n00231:O)                  | NONE(*)(MinSeg1_0)     | 1     |
hour(_n00051:O)                    | NONE(*)(u5_q_3)        | 4     |
minute(_n00031:O)                  | NONE(*)(u3_q_2)        | 4     |
count_18:Q                         | NONE                   | 4     |
clk                                | BUFGP                  | 21    |
msecond10(_n00071:O)               | NONE(*)(u8_q_0)        | 4     |
minute10(_n00041:O)                | NONE(*)(u4_q_0)        | 3     |
second10(_n00021:O)                | NONE(*)(u2_q_0)        | 3     |
-----------------------------------+------------------------+-------+
(*) These 8 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.575ns (Maximum Frequency: 116.618MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 13.486ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\doc\file\seg/_ngo -uc seg.ucf -p
xc2s300e-fg456-6 seg.ngc seg.ngd 

Reading NGO file "G:/doc/file/seg/seg.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "seg.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39800 kilobytes

Writing NGD file "seg.ngd" ...

Writing NGDBUILD log file "seg.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s300efg456-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    8
Logic Utilization:
  Total Number Slice Registers:      49 out of  6,144    1%
    Number used as Flip Flops:                     47
    Number used as Latches:                         2
  Number of 4 input LUTs:           110 out of  6,144    1%
Logic Distribution:
    Number of occupied Slices:                          79 out of  3,072    2%
    Number of Slices containing only related logic:     79 out of     79  100%
    Number of Slices containing unrelated logic:         0 out of     79    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          143 out of  6,144    2%
      Number used as logic:                       110
      Number used as a route-thru:                 33
   Number of bonded IOBs:            19 out of    325    5%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  1,271
Additional JTAG gate count for IOBs:  960
Peak Memory Usage:  68 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "seg_map.mrp" for details.
Completed process "Map".

Mapping Module seg . . .
MAP command line:
map -intstyle ise -p xc2s300e-fg456-6 -cm area -pr b -k 4 -c 100 -tx off -o seg_map.ncd seg.ngd seg.pcf
Mapping Module seg: DONE



Started process "Place & Route".





Constraints file: seg.pcf

Loading device database for application Par from file "seg_map.ncd".
   "seg" is an NCD, version 2.38, device xc2s300e, package fg456, speed -6
Loading device for application Par from file '2s300e.nph' in environment
D:/Xilinx.
Device speed data version:  PRODUCTION 1.17 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            19 out of 325     5%
      Number of LOCed External IOBs   19 out of 19    100%

   Number of SLICEs                   79 out of 3072    2%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989883) REAL time: 3 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
....
Phase 5.8 (Checksum:9d6dc1) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 4 secs 

Writing design to file seg.ncd.

Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 3 secs 


Phase 1: 528 unrouted;       REAL time: 4 secs 

Phase 2: 496 unrouted;       REAL time: 1 mins 2 secs 

Phase 3: 155 unrouted;       REAL time: 1 mins 3 secs 

Phase 4: 0 unrouted;       REAL time: 1 mins 4 secs 

Total REAL time to Router completion: 1 mins 4 secs 
Total CPU time to Router completion: 1 mins 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   13   |  0.061     |  0.489      |
+----------------------------+----------+--------+------------+-------------+
|            minute          |Low-Skew  |    2   |  0.042     |  4.413      |
+----------------------------+----------+--------+------------+-------------+
|            second          |Low-Skew  |    2   |  0.042     |  3.960      |
+----------------------------+----------+--------+------------+-------------+
|          minute10          |   Local  |    2   |  0.000     |  3.592      |
+----------------------------+----------+--------+------------+-------------+
|              hour          |   Local  |    2   |  0.097     |  3.631      |
+----------------------------+----------+--------+------------+-------------+
|            _n0023          |   Local  |    1   |  0.000     |  0.681      |
+----------------------------+----------+--------+------------+-------------+
|         msecond10          |   Local  |    2   |  0.002     |  3.721      |
+----------------------------+----------+--------+------------+-------------+
|            _n0024          |   Local  |    1   |  0.000     |  0.910      |
+----------------------------+----------+--------+------------+-------------+
|         count<18>          |   Local  |    4   |  0.000     |  3.305      |
+----------------------------+----------+--------+------------+-------------+
|          second10          |   Local  |    2   |  0.000     |  3.543      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 mins 6 secs 
Total CPU time to PAR completion: 1 mins 1 secs 

Peak Memory Usage:  72 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file seg.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Jul 02 16:39:33 2002
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module seg . . .
PAR command line: par -w -intstyle ise -ol std -t 1 seg_map.ncd seg.ncd seg.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/doc/file/seg/SEG.vhd in Library work.
Entity <seg> (Architecture <behavioral>) compiled.
Entity <count10> (Architecture <behavioral>) compiled.
Entity <count6> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <seg> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 347: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.