__projnav.log

数字计时器

    Found 1-of-8 decoder for signal <seg_sel>.
    Found 5-bit comparator greatequal for signal <$n0006> created at line 62.
    Found 19-bit up counter for signal <count>.
    Found 1-bit register for signal <enable>.
    Found 5-bit up counter for signal <key_counter>.
    Summary:
	inferred   5 ROM(s).
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Decoder(s).
Unit <seg> synthesized.

WARNING:Xst:524 - All outputs of the instance <u6> of the block <count6> are unconnected in block <seg>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 5
 16x8-bit ROM                      : 3
 16x4-bit ROM                      : 2
# Counters                         : 9
 19-bit up counter                 : 1
 4-bit up counter                  : 5
 5-bit up counter                  : 1
 3-bit up counter                  : 2
# Registers                        : 1
 1-bit register                    : 1
# Latches                          : 2
 1-bit latch                       : 2
# Comparators                      : 1
 5-bit comparator greatequal       : 1
# Decoders                         : 1
 1-of-8 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg> ...
Loading device for application Xst from file '2s300e.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg, actual ratio is 3.
FlipFlop count_13 has been replicated 1 time(s)
FlipFlop count_15 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300epq208-6 

 Number of Slices:                      91  out of   3072     2%  
 Number of Slice Flip Flops:            55  out of   6144     0%  
 Number of 4 input LUTs:               162  out of   6144     2%  
 Number of bonded IOBs:                 20  out of    146    13%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
minute(_n00101:O)                  | NONE(*)(u3_q_0)        | 4     |
hour(_n00121:O)                    | NONE(*)(u5_q_2)        | 4     |
_n0030(_n00301:O)                  | NONE(*)(MinSeg1_0)     | 1     |
second(_n00151:O)                  | NONE(*)(u1_q_3)        | 4     |
msecond(msecond1:O)                | NONE(*)(u7_q_3)        | 4     |
clk                                | BUFGP                  | 21    |
msecond10(_n00141:O)               | NONE(*)(u8_q_0)        | 4     |
_n0031(_n00311:O)                  | NONE(*)(HourSeg1_0)    | 1     |
count_18:Q                         | NONE                   | 6     |
minute10(_n00111:O)                | NONE(*)(u4_q_0)        | 3     |
second10(_n00091:O)                | NONE(*)(u2_q_1)        | 3     |
-----------------------------------+------------------------+-------+
(*) These 9 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.575ns (Maximum Frequency: 116.618MHz)
   Minimum input arrival time before clock: 4.682ns
   Maximum output required time after clock: 13.486ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\doc\file\seg/_ngo -uc seg.ucf -p
xc2s300e-pq208-6 seg.ngc seg.ngd 

Reading NGO file "G:/doc/file/seg/seg.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "seg.ucf" ...
ERROR:NgdBuild:755 - Line 6 in 'seg.ucf': Could not find net(s) 'cs<3>' in the
   design.  To suppress this error specify the correct net name or remove the
   constraint.  The 'Ignore I\O constraints on Invalid Object Names' property
   can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "seg.ucf".

Writing NGDBUILD log file "seg.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


Process interrupted by the user.
ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/doc/file/seg/SEG.vhd in Library work.
ERROR:HDLParsers:3312 - G:/doc/file/seg/SEG.vhd Line 54. Undefined symbol 'enable'.
ERROR:HDLParsers:1209 - G:/doc/file/seg/SEG.vhd Line 54. enable: Undefined symbol (last report in this block)
Entity <count10> (Architecture <behavioral>) compiled.
Entity <count6> (Architecture <behavioral>) compiled.
--> 

Total memory usage is 47824 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/doc/file/seg/SEG.vhd in Library work.
Entity <seg> (Architecture <behavioral>) compiled.
Entity <count10> (Architecture <behavioral>) compiled.
Entity <count6> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <seg> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 347: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 347: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 347: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - G:/doc/file/seg/SEG.vhd line 316: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1561 - G:/doc/file/seg/SEG.vhd line 296: Mux is complete : default of case is discarded
WARNING:Xst:819 - G:/doc/file/seg/SEG.vhd line 270: The following signals are missing in the process sensitivity list:
   MsecSeg1, MsecSeg2, SecSeg1, SecSeg2, MinSeg1, HourSeg1.
Entity <seg> analyzed. Unit <seg> generated.

Analyzing Entity <count10> (Architecture <behavioral>).
Entity <count10> analyzed. Unit <count10> generated.

Analyzing Entity <count6> (Architecture <behavioral>).
Entity <count6> analyzed. Unit <count6> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <count6>.
    Related source file is G:/doc/file/seg/SEG.vhd.
    Found 3-bit up counter for signal <q>.
    Summary:
	inferred   1 Counter(s).
Unit <count6> synthesized.


Synthesizing Unit <count10>.
    Related source file is G:/doc/file/seg/SEG.vhd.
    Found 4-bit up counter for signal <q>.
    Summary:
	inferred   1 Counter(s).
Unit <count10> synthesized.


Synthesizing Unit <seg>.
    Related source file is G:/doc/file/seg/SEG.vhd.
WARNING:Xst:646 - Signal <MinSeg2> is assigned but never used.
WARNING:Xst:646 - Signal <HourSeg2> is assigned but never used.
    Found 16x8-bit ROM for signal <SecSeg1>.
    Found 16x4-bit ROM for signal <$n0021>.
    Found 16x4-bit ROM for signal <$n0022>.
    Found 16x8-bit ROM for signal <MsecSeg1>.
    Found 16x8-bit ROM for signal <MsecSeg2>.
WARNING:Xst:737 - Found 1-bit latch for signal <MinSeg1_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <HourSeg1_0>.
    Found 1-of-8 decoder for signal <seg_sel>.
    Found 19-bit up counter for signal <count>.
    Summary:
	inferred   5 ROM(s).
	inferred   1 Counter(s).
	inferred   1 Decoder(s).
Unit <seg> synthesized.

WARNING:Xst:524 - All outputs of the instance <u6> of the block <count6> are unconnected in block <seg>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 5
 16x8-bit ROM                      : 3
 16x4-bit ROM                      : 2
# Counters                         : 8
 19-bit up counter                 : 1
 4-bit up counter                  : 5
 3-bit up counter                  : 2
# Latches                          : 2
 1-bit latch                       : 2
# Decoders                         : 1
 1-of-8 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg> ...
Loading device for application Xst from file '2s300e.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg, actual ratio is 2.
FlipFlop count_13 has been replicated 1 time(s)
FlipFlop count_15 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300efg456-6 

 Number of Slices:                      82  out of   3072     2%  
 Number of Slice Flip Flops:            49  out of   6144     0%  
 Number of 4 input LUTs:               145  out of   6144     2%  
 Number of bonded IOBs:                 19  out of    329     5%  
 Number of GCLKs:                        1  out of      4    25%