seg.twr

数字计时器

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Release 8.1i Trace I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:\Xilinx\bin\nt\trce.exe -ise seg.ise -intstyle ise -e 3 -l 3 -s 6 -xml seg
seg.ncd -o seg.twr seg.pcf


Design file:              seg.ncd
Physical constraint file: seg.pcf
Device,speed:             xc2v1000,-6 (PRODUCTION 1.121 2005-11-04, STEPPING level 0)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
seg<0>      |    8.989(R)|clk_BUFGP         |   0.000|
seg<1>      |    9.274(R)|clk_BUFGP         |   0.000|
seg<2>      |    9.517(R)|clk_BUFGP         |   0.000|
seg<3>      |    9.239(R)|clk_BUFGP         |   0.000|
seg<4>      |   10.668(R)|clk_BUFGP         |   0.000|
seg<5>      |   10.137(R)|clk_BUFGP         |   0.000|
seg<6>      |    9.608(R)|clk_BUFGP         |   0.000|
seg<7>      |    9.845(R)|clk_BUFGP         |   0.000|
seg_sel<0>  |    8.571(R)|clk_BUFGP         |   0.000|
seg_sel<1>  |    9.313(R)|clk_BUFGP         |   0.000|
seg_sel<2>  |    8.908(R)|clk_BUFGP         |   0.000|
seg_sel<3>  |    9.551(R)|clk_BUFGP         |   0.000|
seg_sel<4>  |    9.318(R)|clk_BUFGP         |   0.000|
seg_sel<5>  |    9.279(R)|clk_BUFGP         |   0.000|
seg_sel<6>  |    9.657(R)|clk_BUFGP         |   0.000|
seg_sel<7>  |    9.398(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    3.851|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Fri Jun 23 14:41:06 2006
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Peak Memory Usage: 112 MB