seg.par

数字计时器

Release 8.1i par I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

CSU-3C87B3C11C6::  Fri Jun 23 14:40:33 2006

par -w -intstyle ise -ol std -t 1 seg_map.ncd seg.ncd seg.pcf 


Constraints file: seg.pcf.
Loading device for application Rf_Device from file '2v1000.nph' in environment D:\Xilinx.
   "seg" is an NCD, version 3.1, device xc2v1000, package fg456, speed -6
This design is using the default stepping level (major silicon revision) for this device (0). Unless your design is
targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any available performance and functional
enhancements for this device. The latest stepping level for this device is '1'. Additional information on "stepping
level" is available at support.xilinx.com.

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.121 2005-11-04".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 16      6%
   Number of External IOBs            20 out of 324     6%
      Number of LOCed IOBs            20 out of 20    100%

   Number of SLICEs                   81 out of 5120    1%


Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98982d) REAL time: 5 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 14 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 14 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 15 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 15 secs 

Phase 7.8
.....
...
........
.....
.....
.
Phase 7.8 (Checksum:9a6c90) REAL time: 15 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 15 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 15 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 15 secs 

Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 15 secs 

Phase 12.24
Phase 12.24 (Checksum:7270df4) REAL time: 15 secs 

Writing design to file seg.ncd


Total REAL time to Placer completion: 16 secs 
Total CPU time to Placer completion: 13 secs 

Starting Router

Phase 1: 592 unrouted;       REAL time: 21 secs 

Phase 2: 575 unrouted;       REAL time: 21 secs 

Phase 3: 122 unrouted;       REAL time: 21 secs 

Phase 4: 122 unrouted; (2239)      REAL time: 21 secs 

Phase 5: 167 unrouted; (0)      REAL time: 21 secs 

Phase 6: 0 unrouted; (347)      REAL time: 22 secs 

Phase 7: 0 unrouted; (347)      REAL time: 22 secs 

Phase 8: 0 unrouted; (347)      REAL time: 22 secs 

Phase 9: 0 unrouted; (345)      REAL time: 23 secs 

Phase 10: 0 unrouted; (345)      REAL time: 23 secs 

Phase 11: 0 unrouted; (345)      REAL time: 23 secs 

WARNING:Route:447 - CLK Net:msecond10 may have excessive skew because 
   2 CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:minute may have excessive skew because 
   2 CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:second may have excessive skew because 
   2 CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:hour may have excessive skew because 
   2 CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:second10 may have excessive skew because 
   2 CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:count<18> may have excessive skew because 
   17 NON-CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 23 secs 
Total CPU time to Router completion: 20 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |     BUFGMUX0P| No   |   12 |  0.006     |  0.865      |
+---------------------+--------------+------+------+------------+-------------+
|            minute10 |         Local|      |    2 |  0.000     |  0.637      |
+---------------------+--------------+------+------+------------+-------------+
|           msecond10 |         Local|      |    2 |  0.233     |  0.878      |
+---------------------+--------------+------+------+------------+-------------+
|              minute |         Local|      |    2 |  0.210     |  0.834      |
+---------------------+--------------+------+------+------------+-------------+
|              second |         Local|      |    2 |  0.320     |  1.201      |
+---------------------+--------------+------+------+------------+-------------+
|           count<18> |         Local|      |   19 |  0.000     |  1.508      |
+---------------------+--------------+------+------+------------+-------------+
|                hour |         Local|      |    2 |  0.230     |  1.345      |
+---------------------+--------------+------+------+------------+-------------+
|              hour10 |         Local|      |    2 |  0.134     |  1.165      |
+---------------------+--------------+------+------+------------+-------------+
|            second10 |         Local|      |    2 |  0.514     |  1.113      |
+---------------------+--------------+------+------+------------+-------------+
|              _n0021 |         Local|      |    1 |  0.000     |  1.097      |
+---------------------+--------------+------+------+------------+-------------+
|              _n0022 |         Local|      |    1 |  0.000     |  0.597      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.597
   The MAXIMUM PIN DELAY IS:                               2.272
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.612

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         542          93           8           0           0           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of  
                                            |            |            | Levels | Slack      |errors     
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net min | N/A        | 1.711ns    | 1      | N/A        | N/A       
  ute10                                     |            |            |        |            |           
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net mse | N/A        | 1.762ns    | 1      | N/A        | N/A       
  cond10                                    |            |            |        |            |           
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net min | N/A        | 1.890ns    | 1      | N/A        | N/A       
  ute                                       |            |            |        |            |           
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net sec | N/A        | 1.877ns    | 1      | N/A        | N/A       
  ond                                       |            |            |        |            |           
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | N/A        | 3.851ns    | 9      | N/A        | N/A       
  _BUFGP                                    |            |            |        |            |           
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net cou | N/A        | 1.701ns    | 1      | N/A        | N/A       
  nt<18>                                    |            |            |        |            |           
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net hou | N/A        | 1.940ns    | 1      | N/A        | N/A       
  r                                         |            |            |        |            |           
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net hou | N/A        | 2.238ns    | 0      | N/A        | N/A       
  r10                                       |            |            |        |            |           
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net sec | N/A        | 2.721ns    | 1      | N/A        | N/A       
  ond10                                     |            |            |        |            |           
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 24 secs 
Total CPU time to PAR completion: 21 secs 

Peak Memory Usage:  127 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 6
Number of info messages: 1

Writing design to file seg.ncd



PAR done!