seg.syr

数字计时器

                                       (47.0% logic, 53.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 79 / 16
-------------------------------------------------------------------------
Offset:              6.874ns (Levels of Logic = 4)
  Source:            count_16 (FF)
  Destination:       seg<4> (PAD)
  Source Clock:      clk rising

  Data Path: count_16 to seg<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             40   0.449   0.846  count_16 (count_16)
     LUT4:I2->O            1   0.347   0.000  count<17>_rn_71_G (N65)
     MUXF5:I1->O           1   0.345   0.414  count<17>_rn_71 (mux_1_count<17>_MUXF58)
     LUT4:I3->O            1   0.347   0.383  count<18>1 (seg_4_OBUF)
     OBUF:I->O                 3.743          seg_4_OBUF (seg<4>)
    ----------------------------------------
    Total                      6.874ns (5.231ns logic, 1.643ns route)
                                       (76.1% logic, 23.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'count_18'
  Total number of paths / destination ports: 28 / 7
-------------------------------------------------------------------------
Offset:              7.446ns (Levels of Logic = 5)
  Source:            u7/q_0 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      count_18 rising

  Data Path: u7/q_0 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.449   0.931  u7/q_0 (u7/q_0)
     LUT4:I0->O            1   0.347   0.548  Mrom_data_Mrom_MsecSeg15 (N32)
     LUT3:I1->O            1   0.347   0.000  count<16>25 (mux_1_N261)
     MUXF5:I0->O           1   0.345   0.000  count<17>_rn_11 (mux_1_count<17>_MUXF512)
     MUXF6:I0->O           1   0.354   0.383  Mmux_seg_seg<0>_seg<0>_rn_3 (seg_6_OBUF)
     OBUF:I->O                 3.743          seg_6_OBUF (seg<6>)
    ----------------------------------------
    Total                      7.446ns (5.585ns logic, 1.861ns route)
                                       (75.0% logic, 25.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'msecond10'
  Total number of paths / destination ports: 28 / 7
-------------------------------------------------------------------------
Offset:              7.308ns (Levels of Logic = 5)
  Source:            u8/q_0 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      msecond10 rising

  Data Path: u8/q_0 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.449   0.931  u8/q_0 (u8/q_0)
     LUT4:I0->O            1   0.347   0.410  Mrom_data_Mrom_MsecSeg25 (N7)
     LUT3:I2->O            1   0.347   0.000  count<16>25 (mux_1_N261)
     MUXF5:I0->O           1   0.345   0.000  count<17>_rn_11 (mux_1_count<17>_MUXF512)
     MUXF6:I0->O           1   0.354   0.383  Mmux_seg_seg<0>_seg<0>_rn_3 (seg_6_OBUF)
     OBUF:I->O                 3.743          seg_6_OBUF (seg<6>)
    ----------------------------------------
    Total                      7.308ns (5.585ns logic, 1.723ns route)
                                       (76.4% logic, 23.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'second10'
  Total number of paths / destination ports: 19 / 7
-------------------------------------------------------------------------
Offset:              7.376ns (Levels of Logic = 5)
  Source:            u2/q_1 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      second10 rising

  Data Path: u2/q_1 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              9   0.449   0.863  u2/q_1 (u2/q_1)
     LUT3:I0->O            2   0.347   0.545  SecSeg2<6>1 (SecSeg2<6>)
     LUT3:I2->O            1   0.347   0.000  count<16>24 (mux_1_N251)
     MUXF5:I1->O           1   0.345   0.000  count<17>_rn_11 (mux_1_count<17>_MUXF512)
     MUXF6:I0->O           1   0.354   0.383  Mmux_seg_seg<0>_seg<0>_rn_3 (seg_6_OBUF)
     OBUF:I->O                 3.743          seg_6_OBUF (seg<6>)
    ----------------------------------------
    Total                      7.376ns (5.585ns logic, 1.791ns route)
                                       (75.7% logic, 24.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'second'
  Total number of paths / destination ports: 31 / 8
-------------------------------------------------------------------------
Offset:              7.446ns (Levels of Logic = 5)
  Source:            u1/q_0 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      second rising

  Data Path: u1/q_0 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.449   0.931  u1/q_0 (u1/q_0)
     LUT4:I0->O            1   0.347   0.548  Mrom_data_Mrom_SecSeg16 (N24)
     LUT3:I1->O            1   0.347   0.000  count<16>24 (mux_1_N251)
     MUXF5:I1->O           1   0.345   0.000  count<17>_rn_11 (mux_1_count<17>_MUXF512)
     MUXF6:I0->O           1   0.354   0.383  Mmux_seg_seg<0>_seg<0>_rn_3 (seg_6_OBUF)
     OBUF:I->O                 3.743          seg_6_OBUF (seg<6>)
    ----------------------------------------
    Total                      7.446ns (5.585ns logic, 1.861ns route)
                                       (75.0% logic, 25.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'minute10'
  Total number of paths / destination ports: 19 / 7
-------------------------------------------------------------------------
Offset:              7.376ns (Levels of Logic = 5)
  Source:            u4/q_1 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      minute10 rising

  Data Path: u4/q_1 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              9   0.449   0.863  u4/q_1 (u4/q_1)
     LUT3:I0->O            2   0.347   0.545  MinSeg2<6>1 (MinSeg2<6>)
     LUT3:I2->O            1   0.347   0.000  count<16>23 (mux_1_N241)
     MUXF5:I0->O           1   0.345   0.000  count<17>_rn_10 (mux_1_count<17>_MUXF511)
     MUXF6:I1->O           1   0.354   0.383  Mmux_seg_seg<0>_seg<0>_rn_3 (seg_6_OBUF)
     OBUF:I->O                 3.743          seg_6_OBUF (seg<6>)
    ----------------------------------------
    Total                      7.376ns (5.585ns logic, 1.791ns route)
                                       (75.7% logic, 24.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'minute'
  Total number of paths / destination ports: 27 / 7
-------------------------------------------------------------------------
Offset:              7.463ns (Levels of Logic = 5)
  Source:            u3/q_1 (FF)
  Destination:       seg<3> (PAD)
  Source Clock:      minute rising

  Data Path: u3/q_1 to seg<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             14   0.449   0.947  u3/q_1 (u3/q_1)
     LUT4:I0->O            1   0.347   0.548  Mrom_data_Mrom__n00193 (N12)
     LUT3:I1->O            1   0.347   0.000  count<16>9 (mux_1_N101)
     MUXF5:I0->O           1   0.345   0.000  count<17>_rn_3 (mux_1_count<17>_MUXF54)
     MUXF6:I1->O           1   0.354   0.383  Mmux_seg_seg<0>_seg<0>_rn_0 (seg_2_OBUF)
     OBUF:I->O                 3.743          seg_2_OBUF (seg<2>)
    ----------------------------------------
    Total                      7.463ns (5.585ns logic, 1.878ns route)
                                       (74.8% logic, 25.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'hour10'
  Total number of paths / destination ports: 19 / 7
-------------------------------------------------------------------------
Offset:              7.359ns (Levels of Logic = 5)
  Source:            u6/q_1 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      hour10 rising

  Data Path: u6/q_1 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              8   0.449   0.845  u6/q_1 (u6/q_1)
     LUT3:I0->O            2   0.347   0.545  HourSeg2<6>1 (HourSeg2<6>)
     LUT3:I2->O            1   0.347   0.000  count<16>22 (mux_1_N231)
     MUXF5:I1->O           1   0.345   0.000  count<17>_rn_10 (mux_1_count<17>_MUXF511)
     MUXF6:I1->O           1   0.354   0.383  Mmux_seg_seg<0>_seg<0>_rn_3 (seg_6_OBUF)
     OBUF:I->O                 3.743          seg_6_OBUF (seg<6>)
    ----------------------------------------
    Total                      7.359ns (5.585ns logic, 1.773ns route)
                                       (75.9% logic, 24.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'hour'
  Total number of paths / destination ports: 27 / 7
-------------------------------------------------------------------------
Offset:              7.463ns (Levels of Logic = 5)
  Source:            u5/q_1 (FF)
  Destination:       seg<3> (PAD)
  Source Clock:      hour rising

  Data Path: u5/q_1 to seg<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             14   0.449   0.947  u5/q_1 (u5/q_1)
     LUT4:I0->O            1   0.347   0.548  Mrom_data_Mrom__n00203 (N16)
     LUT3:I1->O            1   0.347   0.000  count<16>8 (mux_1_N91)
     MUXF5:I1->O           1   0.345   0.000  count<17>_rn_3 (mux_1_count<17>_MUXF54)
     MUXF6:I1->O           1   0.354   0.383  Mmux_seg_seg<0>_seg<0>_rn_0 (seg_2_OBUF)
     OBUF:I->O                 3.743          seg_2_OBUF (seg<2>)
    ----------------------------------------
    Total                      7.463ns (5.585ns logic, 1.878ns route)
                                       (74.8% logic, 25.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_n0022'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.119ns (Levels of Logic = 4)
  Source:            MinSeg1_0 (LATCH)
  Destination:       seg<0> (PAD)
  Source Clock:      _n0022 falling

  Data Path: MinSeg1_0 to seg<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.533   0.415  MinSeg1_0 (MinSeg1_0)
     LUT4:I3->O            1   0.347   0.000  count<16>1 (mux_1_N210)
     MUXF5:I0->O           1   0.345   0.000  count<17> (mux_1_count<17>_MUXF5)
     MUXF6:I1->O           1   0.354   0.383  Mmux_seg_seg<0> (seg_0_OBUF)
     OBUF:I->O                 3.743          seg_0_OBUF (seg<0>)
    ----------------------------------------
    Total                      6.119ns (5.322ns logic, 0.797ns route)
                                       (87.0% logic, 13.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_n0021'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.119ns (Levels of Logic = 4)
  Source:            HourSeg1_0 (LATCH)
  Destination:       seg<0> (PAD)
  Source Clock:      _n0021 falling

  Data Path: HourSeg1_0 to seg<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.533   0.415  HourSeg1_0 (HourSeg1_0)
     LUT4:I3->O            1   0.347   0.000  count<16> (mux_1_N1)
     MUXF5:I1->O           1   0.345   0.000  count<17> (mux_1_count<17>_MUXF5)
     MUXF6:I1->O           1   0.354   0.383  Mmux_seg_seg<0> (seg_0_OBUF)
     OBUF:I->O                 3.743          seg_0_OBUF (seg<0>)
    ----------------------------------------
    Total                      6.119ns (5.322ns logic, 0.797ns route)
                                       (87.0% logic, 13.0% route)

=========================================================================
CPU : 15.50 / 18.98 s | Elapsed : 15.00 / 19.00 s
 
--> 

Total memory usage is 120956 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    9 (   0 filtered)
Number of infos    :   12 (   0 filtered)