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数字计时器

#      MUXF6                       : 7
#      VCC                         : 1
#      XORCY                       : 18
# FlipFlops/Latches                : 53
#      FDR                         : 51
#      LD                          : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 19
#      OBUF                        : 19
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg456-6 

 Number of Slices:                      81  out of   5120     1%  
 Number of Slice Flip Flops:            53  out of  10240     0%  
 Number of 4 input LUTs:               149  out of  10240     1%  
 Number of bonded IOBs:                 20  out of    324     6%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0022(_n00221:O)                  | NONE(*)(MinSeg1_0)     | 1     |
_n0021(_n00211:O)                  | NONE(*)(HourSeg1_0)    | 1     |
msecond10(_n00071:O)               | NONE(*)(u8/q_2)        | 4     |
count_18                           | NONE                   | 4     |
hour(_n00101:O)                    | NONE(*)(u5/q_0)        | 4     |
minute(_n00161:O)                  | NONE(*)(u3/q_3)        | 4     |
second(_n00181:O)                  | NONE(*)(u1/q_0)        | 4     |
hour10(_n00141:O)                  | NONE(*)(u6/q_2)        | 3     |
minute10(_n00151:O)                | NONE(*)(u4/q_0)        | 3     |
second10(_n00041:O)                | NONE(*)(u2/q_0)        | 3     |
clk                                | BUFGP                  | 22    |
-----------------------------------+------------------------+-------+
(*) These 9 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.639ns (Maximum Frequency: 274.820MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.463ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'msecond10'
  Clock period: 2.501ns (frequency: 399.840MHz)
  Total number of paths / destination ports: 26 / 8
-------------------------------------------------------------------------
Delay:               2.501ns (Levels of Logic = 1)
  Source:            u8/q_0 (FF)
  Destination:       u8/q_0 (FF)
  Source Clock:      msecond10 rising
  Destination Clock: msecond10 rising

  Data Path: u8/q_0 to u8/q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.449   0.931  u8/q_0 (u8/q_0)
     LUT4:I0->O            4   0.347   0.553  u8/_n00011 (u8/_n0001)
     FDR:R                     0.222          u8/q_0
    ----------------------------------------
    Total                      2.501ns (1.018ns logic, 1.483ns route)
                                       (40.7% logic, 59.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'count_18'
  Clock period: 2.501ns (frequency: 399.840MHz)
  Total number of paths / destination ports: 26 / 8
-------------------------------------------------------------------------
Delay:               2.501ns (Levels of Logic = 1)
  Source:            u7/q_0 (FF)
  Destination:       u7/q_0 (FF)
  Source Clock:      count_18 rising
  Destination Clock: count_18 rising

  Data Path: u7/q_0 to u7/q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.449   0.931  u7/q_0 (u7/q_0)
     LUT4:I0->O            4   0.347   0.553  u7/_n00011 (u7/_n0001)
     FDR:R                     0.222          u7/q_0
    ----------------------------------------
    Total                      2.501ns (1.018ns logic, 1.483ns route)
                                       (40.7% logic, 59.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'hour'
  Clock period: 2.501ns (frequency: 399.840MHz)
  Total number of paths / destination ports: 26 / 8
-------------------------------------------------------------------------
Delay:               2.501ns (Levels of Logic = 1)
  Source:            u5/q_0 (FF)
  Destination:       u5/q_0 (FF)
  Source Clock:      hour rising
  Destination Clock: hour rising

  Data Path: u5/q_0 to u5/q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.449   0.931  u5/q_0 (u5/q_0)
     LUT4:I0->O            4   0.347   0.553  u5/_n00011 (u5/_n0001)
     FDR:R                     0.222          u5/q_0
    ----------------------------------------
    Total                      2.501ns (1.018ns logic, 1.483ns route)
                                       (40.7% logic, 59.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'minute'
  Clock period: 2.501ns (frequency: 399.840MHz)
  Total number of paths / destination ports: 26 / 8
-------------------------------------------------------------------------
Delay:               2.501ns (Levels of Logic = 1)
  Source:            u3/q_0 (FF)
  Destination:       u3/q_0 (FF)
  Source Clock:      minute rising
  Destination Clock: minute rising

  Data Path: u3/q_0 to u3/q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.449   0.931  u3/q_0 (u3/q_0)
     LUT4:I0->O            4   0.347   0.553  u3/_n00011 (u3/_n0001)
     FDR:R                     0.222          u3/q_0
    ----------------------------------------
    Total                      2.501ns (1.018ns logic, 1.483ns route)
                                       (40.7% logic, 59.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'second'
  Clock period: 2.501ns (frequency: 399.840MHz)
  Total number of paths / destination ports: 26 / 8
-------------------------------------------------------------------------
Delay:               2.501ns (Levels of Logic = 1)
  Source:            u1/q_0 (FF)
  Destination:       u1/q_0 (FF)
  Source Clock:      second rising
  Destination Clock: second rising

  Data Path: u1/q_0 to u1/q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.449   0.931  u1/q_0 (u1/q_0)
     LUT4:I0->O            4   0.347   0.553  u1/_n00011 (u1/_n0001)
     FDR:R                     0.222          u1/q_0
    ----------------------------------------
    Total                      2.501ns (1.018ns logic, 1.483ns route)
                                       (40.7% logic, 59.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'hour10'
  Clock period: 2.399ns (frequency: 416.840MHz)
  Total number of paths / destination ports: 15 / 6
-------------------------------------------------------------------------
Delay:               2.399ns (Levels of Logic = 1)
  Source:            u6/q_2 (FF)
  Destination:       u6/q_0 (FF)
  Source Clock:      hour10 rising
  Destination Clock: hour10 rising

  Data Path: u6/q_2 to u6/q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              8   0.449   0.845  u6/q_2 (u6/q_2)
     LUT3:I0->O            3   0.347   0.535  u6/_n000111 (u6/_n0001)
     FDR:R                     0.222          u6/q_0
    ----------------------------------------
    Total                      2.399ns (1.018ns logic, 1.381ns route)
                                       (42.4% logic, 57.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'minute10'
  Clock period: 2.433ns (frequency: 411.015MHz)
  Total number of paths / destination ports: 15 / 6
-------------------------------------------------------------------------
Delay:               2.433ns (Levels of Logic = 1)
  Source:            u4/q_0 (FF)
  Destination:       u4/q_0 (FF)
  Source Clock:      minute10 rising
  Destination Clock: minute10 rising

  Data Path: u4/q_0 to u4/q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             10   0.449   0.880  u4/q_0 (u4/q_0)
     LUT3:I0->O            3   0.347   0.535  u4/_n000111 (u4/_n0001)
     FDR:R                     0.222          u4/q_0
    ----------------------------------------
    Total                      2.433ns (1.018ns logic, 1.415ns route)
                                       (41.8% logic, 58.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'second10'
  Clock period: 2.433ns (frequency: 411.015MHz)
  Total number of paths / destination ports: 15 / 6
-------------------------------------------------------------------------
Delay:               2.433ns (Levels of Logic = 1)
  Source:            u2/q_0 (FF)
  Destination:       u2/q_0 (FF)
  Source Clock:      second10 rising
  Destination Clock: second10 rising

  Data Path: u2/q_0 to u2/q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             10   0.449   0.880  u2/q_0 (u2/q_0)
     LUT3:I0->O            3   0.347   0.535  u2/_n000111 (u2/_n0001)
     FDR:R                     0.222          u2/q_0
    ----------------------------------------
    Total                      2.433ns (1.018ns logic, 1.415ns route)
                                       (41.8% logic, 58.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 3.639ns (frequency: 274.820MHz)
  Total number of paths / destination ports: 662 / 44
-------------------------------------------------------------------------
Delay:               3.639ns (Levels of Logic = 3)
  Source:            count_18_1 (FF)
  Destination:       count_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: count_18_1 to count_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.449   0.608  count_18_1 (count_18_1)
     LUT4:I0->O            1   0.347   0.414  _n00015_SW0 (N81)
     LUT4_L:I3->LO         1   0.347   0.127  _n00015 (N34)
     LUT4:I2->O           22   0.347   0.778  _n0001155 (_n0001)
     FDR:R                     0.222          count_0
    ----------------------------------------
    Total                      3.639ns (1.712ns logic, 1.927ns route)