seg.syr

数字计时器

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 3.20 s | Elapsed : 0.00 / 4.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 3.20 s | Elapsed : 0.00 / 4.00 s
 
--> Reading design: seg.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "seg.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "seg"
Output Format                      : NGC
Target Device                      : xc2v1000-6-fg456

---- Source Options
Top Module Name                    : seg
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : seg.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/seg is now defined in a different file: was E:/科瑞特产品/Create-SOPC系列/Create-SOPC1000X片上系统教学开发平台/实验代码/lab4/SEG.vhd, now is E:/FPGA/Exp4-Clock/SEG.vhd
WARNING:HDLParsers:3215 - Unit work/seg/Behavioral is now defined in a different file: was E:/科瑞特产品/Create-SOPC系列/Create-SOPC1000X片上系统教学开发平台/实验代码/lab4/SEG.vhd, now is E:/FPGA/Exp4-Clock/SEG.vhd
WARNING:HDLParsers:3215 - Unit work/count10 is now defined in a different file: was E:/科瑞特产品/Create-SOPC系列/Create-SOPC1000X片上系统教学开发平台/实验代码/lab4/SEG.vhd, now is E:/FPGA/Exp4-Clock/SEG.vhd
WARNING:HDLParsers:3215 - Unit work/count10/Behavioral is now defined in a different file: was E:/科瑞特产品/Create-SOPC系列/Create-SOPC1000X片上系统教学开发平台/实验代码/lab4/SEG.vhd, now is E:/FPGA/Exp4-Clock/SEG.vhd
WARNING:HDLParsers:3215 - Unit work/count6 is now defined in a different file: was E:/科瑞特产品/Create-SOPC系列/Create-SOPC1000X片上系统教学开发平台/实验代码/lab4/SEG.vhd, now is E:/FPGA/Exp4-Clock/SEG.vhd
WARNING:HDLParsers:3215 - Unit work/count6/Behavioral is now defined in a different file: was E:/科瑞特产品/Create-SOPC系列/Create-SOPC1000X片上系统教学开发平台/实验代码/lab4/SEG.vhd, now is E:/FPGA/Exp4-Clock/SEG.vhd
Compiling vhdl file "E:/FPGA/Exp4-Clock/SEG.vhd" in Library work.
Entity <seg> compiled.
Entity <seg> (Architecture <behavioral>) compiled.
Entity <count10> compiled.
Entity <count10> (Architecture <behavioral>) compiled.
Entity <count6> compiled.
Entity <count6> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <seg> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - "E:/FPGA/Exp4-Clock/SEG.vhd" line 297: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/FPGA/Exp4-Clock/SEG.vhd" line 328: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/FPGA/Exp4-Clock/SEG.vhd" line 297: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/FPGA/Exp4-Clock/SEG.vhd" line 328: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/FPGA/Exp4-Clock/SEG.vhd" line 297: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/FPGA/Exp4-Clock/SEG.vhd" line 328: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/FPGA/Exp4-Clock/SEG.vhd" line 297: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "E:/FPGA/Exp4-Clock/SEG.vhd" line 297: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1561 - "E:/FPGA/Exp4-Clock/SEG.vhd" line 277: Mux is complete : default of case is discarded
WARNING:Xst:819 - "E:/FPGA/Exp4-Clock/SEG.vhd" line 251: The following signals are missing in the process sensitivity list:
   MsecSeg1, MsecSeg2, SecSeg1, SecSeg2, MinSeg1, MinSeg2, HourSeg1, HourSeg2.
Entity <seg> analyzed. Unit <seg> generated.

Analyzing Entity <count10> (Architecture <behavioral>).
Entity <count10> analyzed. Unit <count10> generated.

Analyzing Entity <count6> (Architecture <behavioral>).
Entity <count6> analyzed. Unit <count6> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <count6>.
    Related source file is "E:/FPGA/Exp4-Clock/SEG.vhd".
    Found 3-bit up counter for signal <q>.
    Summary:
	inferred   1 Counter(s).
Unit <count6> synthesized.


Synthesizing Unit <count10>.
    Related source file is "E:/FPGA/Exp4-Clock/SEG.vhd".
    Found 4-bit up counter for signal <q>.
    Summary:
	inferred   1 Counter(s).
Unit <count10> synthesized.


Synthesizing Unit <seg>.
    Related source file is "E:/FPGA/Exp4-Clock/SEG.vhd".
    Found 16x8-bit ROM for signal <MsecSeg2>.
    Found 16x4-bit ROM for signal <$n0019>.
    Found 4x1-bit ROM for signal <MinSeg1<7>>.
    Found 16x8-bit ROM for signal <SecSeg1>.
    Found 16x4-bit ROM for signal <$n0020>.
    Found 4x1-bit ROM for signal <HourSeg1<7>>.
    Found 16x8-bit ROM for signal <MsecSeg1>.
WARNING:Xst:737 - Found 1-bit latch for signal <HourSeg1_0>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <MinSeg1_0>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch.
    Found 8-bit 8-to-1 multiplexer for signal <seg>.
    Found 1-of-8 decoder for signal <seg_sel>.
    Found 19-bit up counter for signal <count>.
    Summary:
	inferred   7 ROM(s).
	inferred   1 Counter(s).
	inferred   8 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <seg> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 7
 16x4-bit ROM                                          : 2
 16x8-bit ROM                                          : 3
 4x1-bit ROM                                           : 2
# Counters                                             : 9
 19-bit up counter                                     : 1
 3-bit up counter                                      : 3
 4-bit up counter                                      : 5
# Latches                                              : 2
 1-bit latch                                           : 2
# Multiplexers                                         : 1
 8-bit 8-to-1 multiplexer                              : 1
# Decoders                                             : 1
 1-of-8 decoder                                        : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 7
 16x4-bit ROM                                          : 2
 16x8-bit ROM                                          : 3
 4x1-bit ROM                                           : 2
# Counters                                             : 9
 19-bit up counter                                     : 1
 3-bit up counter                                      : 3
 4-bit up counter                                      : 5
# Latches                                              : 2
 1-bit latch                                           : 2
# Multiplexers                                         : 1
 8-bit 8-to-1 multiplexer                              : 1
# Decoders                                             : 1
 1-of-8 decoder                                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '2v1000.nph' in environment D:\Xilinx.

Optimizing unit <seg> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg, actual ratio is 1.
FlipFlop count_16 has been replicated 1 time(s)
FlipFlop count_17 has been replicated 1 time(s)
FlipFlop count_18 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : seg.ngr
Top Level Output File Name         : seg
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 20

Cell Usage :
# BELS                             : 218
#      GND                         : 1
#      INV                         : 9
#      LUT1_L                      : 18
#      LUT2                        : 8
#      LUT3                        : 57
#      LUT4                        : 65
#      LUT4_L                      : 1
#      MUXCY                       : 18
#      MUXF5                       : 15