_info

四位全家器的VHDL语言模块

m255
13
cModel Technology
dD:\Program Files\Modeltech_6.1b\examples
Efull_adder
w1148200920
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dF:\FPGA exp\FullAdder
FF:/FPGA exp/FullAdder/top.vhd
l0
L4
VGb<1h_SN6K6GomNBRE60f3
OE;C;6.1b;31
32
o-work work -2002 -explicit
tExplicit 1 GenerateLoopIterationMax 100000
Abehavioral
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work full_adder Gb<1h_SN6K6GomNBRE60f3
l9
L8
VP9?I]h72HdReOC3NI`DEj3
OE;C;6.1b;31
32
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-work work -2002 -explicit
tExplicit 1 GenerateLoopIterationMax 100000