fulladd.acc

用于实现两个数相加的vhdl代码

# Accolade project file saved 07-02-2006 23:39:14
$Version "5.15a"
$OPTION "CompileOrder=1"
$OPTION "CompileOutOfDate=1"
$OPTION "CompileUse="
$OPTION "CompileVHDL93=1"
$OPTION "LinkUpdateObject=1"
$OPTION "LinkOutOfDate=1"
$OPTION "LinkEntity="
$OPTION "LinkArchitecture="
$OPTION "LinkSDF="
$OPTION "LinkSDFInstance="
$OPTION "MinAvgMax=1"
$OPTION "LinkSourceLevel=1"
$OPTION "RunUpdateExec=1"
$OPTION "RunSource=1"
$OPTION "RunToTime=840"
$OPTION "RunUnit=ns"
$OPTION "RunStepTime=40"
$OPTION "RunDepth=3"
$OPTION "RunVectorFormat=decimal"
$OPTION "SnapCursor=1"
$OPTION "SynthOrder=0"
$OPTION "SynthAnalyze=0"
$OPTION "SynthVerbose=0"
$OPTION "SynthNumeric=0"
$OPTION "SynthSynopsys=0"
$OPTION "SynthModule=1"
$OPTION "SynthEntity="
$OPTION "SynthArchitecture="
$OPTION "SynthFamily=Actel, ACT-3 Series (EDIF)"
$OPTION "SynthFamilyID="
$OPTION "SynthPartID="
$OPTION "SynthFileExt="
$OPTION "SynthOptTarget="
$OPTION "SynthDeviceName="
$OPTION "SynthLevel=5"
$OPTION "SynthXopt=3"
$OPTION "SynthBUFG="
$OPTION "SynthGoal="
$OPTION "SynthPterms="
$OPTION "SynthLibraryMapping="
$OPTION "OptSoftware=2"
$OPTION "OptCompress=1"
$OPTION "OptFlatten=0"
$OPTION "OptBuffers=0"
$OPTION "OptIncremental=1"
$OPTION "OptFormat="
$OPTION "OptPriority=speed"
$OPTION "OptCircuitName="
$OPTION "OptDontFlatten="
$OPTION "OptDontCompress="
$OPTION "ProjectPath=E:\\ѧϰ\\Multisi\\vhdl\\Examples\\fulladd\\"
$FILES
($MODULE "TESTADD.VHD" WORK ""
 ($ENTITY TESTBNCH "TESTADD.VHD" WORK 8
  USE FULLADD
  ($ARCHITECTURE STIMULUS "TESTADD.VHD" WORK 11
   USE FULLADD
   ($COMPONENT DUT "TESTADD.VHD" WORK 31
    ($ENTITY FULLADDER "FULLADD.VHD" WORK 14
    )
   )
  )
 )
$MODULE "FULLADD.VHD" WORK ""
 ($ENTITY FULLADDER "FULLADD.VHD" WORK 14
  ($ARCHITECTURE CONCURRENT "FULLADD.VHD" WORK 22
  )
 )
)