fulladd.vhd

用于实现两个数相加的vhdl代码

-------------------------------------------------------
-- Full adder.
--
-- This project demonstrates the use of concurrent
-- statements in VHDL., and demonstrates the simplest
-- form of VHDL design description. There are no
-- external libraries specified.
--
-- The test bench for this example (TESTADD.VHD) expects
-- that this module (FULLADD.VHD) be compiled into the
-- WORK library.
--

entity FULLADDER is
    port (X: in bit;
          Y: in bit;
          Cin: in bit;
          Cout: out bit;
          Sum: out bit);
end FULLADDER;

architecture CONCURRENT of FULLADDER is
begin

    -- Concurrent statements go here...

    Sum <= X xor Y xor Cin;
    Cout <= (X and Y) or (X and Cin) or (Y and Cin);

end CONCURRENT;