eqiangdaqi.rpt
来自「VHDL电子抢答器的实现。有多个文件」· RPT 代码 · 共 1,129 行 · 第 1/5 页
RPT
1,129 行
- 1 - A 02 AND2 0 3 0 3 |JIAJIANFEN1:94|:65
- 1 - A 10 OR2 0 2 0 2 |JIAJIANFEN1:94|:161
- 7 - A 01 OR2 ! 0 4 0 1 |JIAJIANFEN1:94|:231
- 8 - A 10 OR2 0 4 0 1 |JIAJIANFEN1:94|:266
- 6 - A 10 OR2 0 4 0 1 |JIAJIANFEN1:94|:267
- 6 - A 01 OR2 ! 0 4 0 1 |JIAJIANFEN1:94|:275
- 8 - A 01 OR2 ! 0 4 0 1 |JIAJIANFEN1:94|:276
- 4 - A 01 OR2 0 4 0 1 |JIAJIANFEN1:94|:280
- 5 - A 01 OR2 0 4 0 1 |JIAJIANFEN1:94|:283
- 7 - A 10 AND2 s 0 2 0 1 |JIAJIANFEN1:94|~284~1
- 5 - A 10 OR2 ! 0 4 0 1 |JIAJIANFEN1:94|:292
- 5 - E 09 DFFE 2 1 0 8 |LOCK:8|:7
- 1 - E 09 DFFE 2 1 0 8 |LOCK:8|:9
- 2 - E 09 DFFE 2 1 0 8 |LOCK:8|:11
- 3 - E 09 DFFE 2 1 0 8 |LOCK:8|:13
- 8 - E 09 DFFE 1 1 0 18 |LOCK:8|:15
- 5 - E 19 OR2 0 2 0 1 |M100:14|LPM_ADD_SUB:85|addcore:adder|pcarry1
- 8 - E 02 OR2 0 2 0 3 |M100:14|LPM_ADD_SUB:90|addcore:adder|pcarry1
- 1 - E 13 DFFE 1 3 0 1 |M100:14|:4
- 5 - E 05 DFFE 1 4 0 3 |M100:14|dw3 (|M100:14|:18)
- 3 - E 05 DFFE 0 4 0 3 |M100:14|dw2 (|M100:14|:19)
- 4 - E 02 DFFE 0 4 0 2 |M100:14|dw1 (|M100:14|:20)
- 1 - E 02 DFFE 1 3 0 3 |M100:14|dw0 (|M100:14|:21)
- 5 - E 16 DFFE 0 3 0 3 |M100:14|gw3 (|M100:14|:22)
- 1 - E 19 DFFE 0 4 0 2 |M100:14|gw2 (|M100:14|:23)
- 7 - E 19 DFFE 0 4 0 3 |M100:14|gw1 (|M100:14|:24)
- 2 - E 06 DFFE 1 4 0 5 |M100:14|gw0 (|M100:14|:25)
- 6 - E 16 OR2 ! 0 2 0 6 |M100:14|:73
- 8 - E 05 OR2 ! 0 3 0 6 |M100:14|:74
- 4 - E 05 OR2 0 3 0 1 |M100:14|:112
- 7 - E 06 OR2 0 2 0 1 |M100:14|:175
- 2 - E 19 OR2 s 0 4 0 2 |M100:14|~287~1
- 4 - E 16 OR2 s 1 3 0 1 |M100:14|~287~2
- 6 - E 19 AND2 s 0 2 0 2 |M100:14|~293~1
- 2 - E 16 OR2 2 2 0 1 |SELLING1:34|:256
- 1 - E 16 OR2 2 2 0 1 |SELLING1:34|:258
- 3 - E 16 OR2 2 2 0 3 |SELLING1:34|:262
- 3 - E 20 OR2 2 2 0 1 |SELLING1:34|:274
- 2 - E 20 OR2 2 2 0 1 |SELLING1:34|:276
- 1 - E 20 OR2 2 2 0 3 |SELLING1:34|:277
- 4 - E 19 OR2 2 2 0 1 |SELLING1:34|:289
- 3 - E 19 OR2 2 2 0 1 |SELLING1:34|:291
- 8 - E 19 OR2 2 2 0 2 |SELLING1:34|:292
- 4 - E 06 OR2 2 2 0 1 |SELLING1:34|:304
- 1 - E 06 OR2 2 2 0 1 |SELLING1:34|:306
- 5 - E 06 OR2 2 2 0 3 |SELLING1:34|:307
- 5 - E 12 OR2 2 2 0 1 |SELLING1:34|:316
- 7 - E 12 OR2 2 2 0 1 |SELLING1:34|:318
- 1 - E 05 OR2 2 2 0 3 |SELLING1:34|:322
- 7 - E 05 OR2 2 2 0 1 |SELLING1:34|:324
- 3 - E 12 OR2 2 2 0 1 |SELLING1:34|:331
- 2 - E 03 OR2 2 2 0 1 |SELLING1:34|:333
- 2 - E 05 OR2 2 2 0 3 |SELLING1:34|:337
- 6 - E 05 OR2 2 2 0 1 |SELLING1:34|:339
- 3 - E 03 OR2 2 2 0 1 |SELLING1:34|:346
- 8 - E 03 OR2 2 2 0 1 |SELLING1:34|:348
- 3 - E 02 OR2 2 2 0 2 |SELLING1:34|:352
- 2 - E 10 OR2 2 2 0 1 |SELLING1:34|:354
- 6 - E 02 OR2 2 2 0 1 |SELLING1:34|:361
- 5 - E 02 OR2 2 2 0 1 |SELLING1:34|:363
- 2 - E 02 OR2 2 2 0 3 |SELLING1:34|:367
- 7 - E 02 OR2 2 2 0 1 |SELLING1:34|:369
- 4 - C 07 DFFE 1 2 0 6 |SHAOMIAODE:59|Q2 (|SHAOMIAODE:59|:36)
- 7 - C 07 DFFE 1 1 0 7 |SHAOMIAODE:59|Q1 (|SHAOMIAODE:59|:37)
- 5 - C 07 DFFE 1 0 0 8 |SHAOMIAODE:59|Q0 (|SHAOMIAODE:59|:38)
- 2 - C 07 AND2 0 3 1 10 |SHAOMIAODE:59|:88
- 1 - C 07 AND2 0 3 1 6 |SHAOMIAODE:59|:92
- 8 - C 07 AND2 0 3 1 6 |SHAOMIAODE:59|:96
- 3 - C 07 AND2 0 3 1 6 |SHAOMIAODE:59|:100
- 6 - C 11 AND2 0 3 1 6 |SHAOMIAODE:59|:104
- 6 - C 07 AND2 0 3 1 6 |SHAOMIAODE:59|:153
- 4 - E 01 OR2 0 4 0 1 |SHAOMIAODE:59|:304
- 1 - E 01 OR2 0 3 0 1 |SHAOMIAODE:59|:310
- 6 - B 11 OR2 0 4 0 5 |SHAOMIAODE:59|:322
- 8 - E 01 OR2 ! 0 4 0 1 |SHAOMIAODE:59|:337
- 5 - E 01 OR2 0 3 0 1 |SHAOMIAODE:59|:339
- 2 - E 07 OR2 ! 0 3 0 1 |SHAOMIAODE:59|:340
- 3 - E 07 OR2 ! 0 4 0 2 |SHAOMIAODE:59|:346
- 4 - B 03 OR2 ! 0 4 0 18 |SHAOMIAODE:59|:349
- 2 - B 03 OR2 s ! 0 4 0 1 |SHAOMIAODE:59|~350~1
- 5 - E 07 OR2 0 4 0 1 |SHAOMIAODE:59|:358
- 7 - E 07 OR2 0 3 0 1 |SHAOMIAODE:59|:361
- 4 - E 07 OR2 0 3 0 3 |SHAOMIAODE:59|:364
- 7 - B 03 OR2 0 2 0 1 |SHAOMIAODE:59|:367
- 5 - B 03 OR2 s 0 4 0 1 |SHAOMIAODE:59|~370~1
- 7 - B 11 OR2 ! 0 4 0 4 |SHAOMIAODE:59|:370
- 2 - E 01 OR2 0 4 0 1 |SHAOMIAODE:59|:379
- 6 - E 06 OR2 0 3 0 1 |SHAOMIAODE:59|:382
- 6 - E 07 OR2 0 3 0 2 |SHAOMIAODE:59|:385
- 6 - B 03 OR2 ! 0 4 0 4 |SHAOMIAODE:59|:391
- 4 - E 03 OR2 0 2 0 1 |S10:36|LPM_ADD_SUB:51|addcore:adder|pcarry1
- 1 - E 03 OR2 0 3 0 2 |S10:36|LPM_ADD_SUB:51|addcore:adder|pcarry2
- 8 - E 13 DFFE 1 3 0 1 |S10:36|:4
- 5 - E 04 DFFE 0 3 0 3 |S10:36|dw3 (|S10:36|:14)
- 5 - E 03 DFFE 0 4 0 2 |S10:36|dw2 (|S10:36|:15)
- 7 - E 03 DFFE 0 4 0 3 |S10:36|dw1 (|S10:36|:16)
- 6 - E 03 DFFE 1 3 0 4 |S10:36|dw0 (|S10:36|:17)
- 4 - E 04 OR2 ! 0 2 0 5 |S10:36|:40
- 1 - E 04 OR2 1 3 0 1 |S10:36|:106
- 3 - E 11 OR2 0 4 0 1 |S10:43|LPM_ADD_SUB:51|addcore:adder|:69
- 1 - E 11 DFFE 2 2 1 1 |S10:43|:4
- 7 - E 11 DFFE 2 3 0 4 |S10:43|dw3 (|S10:43|:14)
- 8 - E 11 DFFE 1 3 0 4 |S10:43|dw2 (|S10:43|:15)
- 2 - E 11 DFFE 1 2 0 4 |S10:43|dw1 (|S10:43|:16)
- 5 - E 11 DFFE 2 2 0 6 |S10:43|dw0 (|S10:43|:17)
- 4 - E 11 OR2 ! 0 4 0 4 |S10:43|:40
- 6 - E 11 AND2 s 1 2 0 2 |S10:43|~152~1
- 3 - B 03 OR2 ! 0 4 0 1 |TANSF:13|:188
- 6 - E 09 OR2 s 3 0 0 1 ~10~1
- 4 - E 13 OR2 0 4 1 0 :30
- 7 - E 09 OR2 1 2 0 1 :52
- 6 - E 24 AND2 2 0 0 32 :74
- 4 - C 14 AND2 2 0 0 4 :79
- 1 - F 02 AND2 ! 2 0 0 4 :81
- 1 - F 07 OR2 2 0 0 6 :82
- 1 - B 03 OR2 0 4 0 4 :98
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\qingdaqi1\eqiangdaqi.rpt
eqiangdaqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 11/ 48( 22%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 21/ 96( 21%) 18/ 48( 37%) 14/ 48( 29%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
C: 5/ 96( 5%) 3/ 48( 6%) 1/ 48( 2%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
D: 9/ 96( 9%) 8/ 48( 16%) 0/ 48( 0%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
E: 42/ 96( 43%) 31/ 48( 64%) 16/ 48( 33%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
F: 9/ 96( 9%) 0/ 48( 0%) 12/ 48( 25%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 8/24( 33%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 6/24( 25%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\qingdaqi1\eqiangdaqi.rpt
eqiangdaqi
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 32 :74
INPUT 23 clk
DFF 9 |CHOOSE:11|:3
LCELL 4 :79
INPUT 3 clk1
LCELL 1 :52
Device-Specific Information: d:\qingdaqi1\eqiangdaqi.rpt
eqiangdaqi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 16 clr
INPUT 10 start
INPUT 4 t
Device-Specific Information: d:\qingdaqi1\eqiangdaqi.rpt
eqiangdaqi
** EQUATIONS **
clk : INPUT;
clk1 : INPUT;
clr : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
ff : INPUT;
jia : INPUT;
jian : INPUT;
p : INPUT;
start : INPUT;
stop : INPUT;
s0 : INPUT;
s1 : INPUT;
t : INPUT;
ting : INPUT;
zf : INPUT;
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