eqiangdaqi.rpt
来自「VHDL电子抢答器的实现。有多个文件」· RPT 代码 · 共 1,129 行 · 第 1/5 页
RPT
1,129 行
***** Logic for device 'eqiangdaqi' compiled without errors.
Device: EPF10K20TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S G G G G V S S S S S S S S S S S S
E E E E E G E E E E V E E E E G N N N N C E E E E E E V E E E E E E
R R R R R N R R R R C R R R R N c D D D D C R R R R R R C R R R R R R
V V V V V D V V V V C V V V V D l I I I I I c V V V V V V C V V V V V V
E E E E E I E E E E I E E E E I k N N N N N l E E E E E E I E E E E E E
D D D D D O D D D D O D D D D O 1 T T T T T k D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | ss3
ss2 | 8 101 | RESERVED
alarm | 9 100 | ss5
RESERVED | 10 99 | ss1
RESERVED | 11 98 | ss0
RESERVED | 12 97 | RESERVED
RESERVED | 13 96 | ss4
RESERVED | 14 95 | ff
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
dw | 17 92 | zf
RESERVED | 18 91 | clr
RESERVED | 19 EPF10K20TC144-3 90 | t
RESERVED | 20 89 | ting
T40 | 21 88 | s1
T41 | 22 87 | s0
T42 | 23 86 | start
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
T43 | 26 83 | p
T30 | 27 82 | stop
T31 | 28 81 | jian
T32 | 29 80 | jia
T33 | 30 79 | d4
T20 | 31 78 | d3
T21 | 32 77 | ^MSEL0
T22 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
T23 | 36 73 | d2
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
T T T G T R q q V q q q q G q V V G G G G G R R V R R R R G R R R R V d
1 1 1 N 1 E 0 1 C 2 3 4 5 N 6 C C N N N N N E E C E E E E N E E E E C 1
0 1 2 D 3 S C D C C D D D D D S S C S S S S D S S S S C
I E I I I I I I I I I E E I E E E E I E E E E I
O R O O N N N N N N N R R O R R R R O R R R R O
V T T T T T T T V V V V V V V V V V
E E E E E E E E E E E
D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\qingdaqi1\eqiangdaqi.rpt
eqiangdaqi
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 9/22( 40%)
A2 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
A10 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
B1 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
B3 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
B7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B9 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
B10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B11 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
B13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B14 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
B16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B17 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
B18 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
B19 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
B22 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
B23 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 4/22( 18%)
C7 8/ 8(100%) 7/ 8( 87%) 3/ 8( 37%) 1/2 0/2 1/22( 4%)
C11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
D1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
D2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
D4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
D9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
E2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
E3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
E4 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
E5 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
E6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 13/22( 59%)
E7 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 16/22( 72%)
E9 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 2/2 1/2 6/22( 27%)
E10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
E11 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 3/22( 13%)
E12 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
E13 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
E15 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
E16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
E19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
E20 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
E21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
E24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
F7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
F13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F14 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
F18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F23 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 49/96 ( 51%)
Total logic cells used: 269/1152 ( 23%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.34/4 ( 83%)
Total fan-in: 901/4608 ( 19%)
Total input pins required: 18
Total input I/O cell registers required: 0
Total output pins required: 31
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 269
Total flipflops required: 66
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 37/1152 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 2 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18/0
B: 8 0 8 0 0 0 1 0 8 1 7 0 0 1 8 0 8 2 8 8 0 0 8 1 0 77/0
C: 0 0 0 0 0 0 8 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 10/0
D: 8 1 0 8 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18/0
E: 8 8 8 3 8 8 8 0 8 8 8 8 0 8 0 7 8 0 0 8 3 8 0 0 1 126/0
F: 0 1 0 0 0 0 1 0 0 0 0 0 0 1 8 0 0 0 1 0 0 0 0 8 0 20/0
Total: 32 12 16 11 8 8 18 0 17 17 16 8 0 10 17 7 16 2 9 16 3 8 8 9 1 269/0
Device-Specific Information: d:\qingdaqi1\eqiangdaqi.rpt
eqiangdaqi
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
122 - - - 13 INPUT 0 0 0 23 clk
128 - - - 13 INPUT 0 0 0 3 clk1
91 - - C -- INPUT 0 0 0 16 clr
72 - - - 03 INPUT 0 0 0 2 d1
73 - - - 01 INPUT 0 0 0 2 d2
78 - - F -- INPUT 0 0 0 2 d3
79 - - F -- INPUT 0 0 0 2 d4
95 - - B -- INPUT 0 0 0 17 ff
80 - - F -- INPUT 0 0 0 1 jia
81 - - F -- INPUT 0 0 0 1 jian
83 - - E -- INPUT 0 0 0 18 p
86 - - E -- INPUT 0 0 0 10 start
82 - - E -- INPUT 0 0 0 1 stop
87 - - E -- INPUT 0 0 0 28 s0
88 - - D -- INPUT 0 0 0 28 s1
90 - - C -- INPUT 0 0 0 4 t
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