machinectl.v

verilog数字系统设计教程 所有例题的源程

//?????
//------------------------------------------------------------------------------
module machinectl( ena, fetch, rst);
output  ena;
input  fetch, rst;
reg ena;

always @(posedge fetch or posedge rst)
begin
if(rst)
ena<=0;
else
ena<=1;
end

endmodule
//----------------------------------------------------------------------------