counterx.tan.rpt

通过VHDL语言编写的计数器程序,可以在一吗器显示管上分段显示小时,分,秒,并且可以分别清零

; N/A   ; None         ; 1.300 ns   ; clear  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A   ; None         ; 1.300 ns   ; clear  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A   ; None         ; 1.300 ns   ; clear  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A   ; None         ; 1.300 ns   ; clear  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
; N/A   ; None         ; 1.300 ns   ; d[3]   ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A   ; None         ; 1.100 ns   ; ld     ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A   ; None         ; 1.100 ns   ; ld     ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A   ; None         ; 1.100 ns   ; ld     ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A   ; None         ; 1.100 ns   ; ld     ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
+-------+--------------+------------+--------+-----------------------------------------------------------+----------+


+--------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                ;
+-------+--------------+------------+-----------------------------------------------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From                                                      ; To    ; From Clock ;
+-------+--------------+------------+-----------------------------------------------------------+-------+------------+
; N/A   ; None         ; 11.400 ns  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; qa[2] ; clk        ;
; N/A   ; None         ; 10.400 ns  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; qa[0] ; clk        ;
; N/A   ; None         ; 10.400 ns  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; qa[1] ; clk        ;
; N/A   ; None         ; 10.400 ns  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; qa[3] ; clk        ;
+-------+--------------+------------+-----------------------------------------------------------+-------+------------+


+-------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                      ;
+---------------+-------------+-----------+--------+-----------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                                                        ; To Clock ;
+---------------+-------------+-----------+--------+-----------------------------------------------------------+----------+
; N/A           ; None        ; 0.800 ns  ; ld     ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; ld     ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; ld     ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; ld     ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
; N/A           ; None        ; 0.600 ns  ; d[2]   ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; 0.600 ns  ; clear  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A           ; None        ; 0.600 ns  ; clear  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; 0.600 ns  ; clear  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A           ; None        ; 0.600 ns  ; clear  ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
; N/A           ; None        ; 0.600 ns  ; d[3]   ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A           ; None        ; 0.500 ns  ; enable ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A           ; None        ; 0.500 ns  ; enable ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; 0.500 ns  ; enable ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A           ; None        ; 0.500 ns  ; enable ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
; N/A           ; None        ; -3.400 ns ; d[1]   ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A           ; None        ; -3.400 ns ; d[0]   ; lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
+---------------+-------------+-----------+--------+-----------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition
    Info: Processing started: Fri Jan 01 06:12:45 1999
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off counterx -c counterx
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 200.0 MHz between source register "lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" and destination register "lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3]"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.400 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F4; Fanout = 3; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = LC1_F4; Fanout = 2; COMB Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT'
            Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 0.400 ns; Loc. = LC2_F4; Fanout = 3; COMB Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT'
            Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 0.600 ns; Loc. = LC3_F4; Fanout = 1; COMB Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT'
            Info: 5: + IC(0.000 ns) + CELL(0.800 ns) = 1.400 ns; Loc. = LC4_F4; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 1.400 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_F4; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
            Info: - Longest clock path from clock "clk" to source register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_F4; Fanout = 3; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: + Micro clock to output delay of source is 0.500 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1]" (data pin = "d[1]", clock pin = "clk") is 5.300 ns
    Info: + Longest pin to register delay is 7.100 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_78; Fanout = 1; PIN Node = 'd[1]'
        Info: 2: + IC(1.200 ns) + CELL(1.000 ns) = 7.100 ns; Loc. = LC2_F4; Fanout = 3; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
        Info: Total cell delay = 5.900 ns ( 83.10 % )
        Info: Total interconnect delay = 1.200 ns ( 16.90 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_F4; Fanout = 3; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "clk" to destination pin "qa[2]" through register "lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2]" is 11.400 ns
    Info: + Longest clock path from clock "clk" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_F4; Fanout = 4; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_F4; Fanout = 4; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
        Info: 2: + IC(2.200 ns) + CELL(6.300 ns) = 8.500 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'qa[2]'
        Info: Total cell delay = 6.300 ns ( 74.12 % )
        Info: Total interconnect delay = 2.200 ns ( 25.88 % )
Info: th for register "lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" (data pin = "ld", clock pin = "clk") is 0.800 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_F4; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 2.900 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 5; PIN Node = 'ld'
        Info: 2: + IC(0.100 ns) + CELL(0.800 ns) = 2.900 ns; Loc. = LC4_F4; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.800 ns ( 96.55 % )
        Info: Total interconnect delay = 0.100 ns ( 3.45 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jan 01 06:12:49 1999
    Info: Elapsed time: 00:00:05