counterx.map.qmsg

通过VHDL语言编写的计数器程序,可以在一吗器显示管上分段显示小时,分,秒,并且可以分别清零

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 27 03:08:19 2006 " "Info: Processing started: Sat May 27 03:08:19 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counterx -c counterx " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off counterx -c counterx" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counterx.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counterx.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counterx-a " "Info: Found design unit 1: counterx-a" {  } { { "counterx.vhd" "" { Text "E:/数字逻辑/counterx/counterx.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 counterx " "Info: Found entity 1: counterx" {  } { { "counterx.vhd" "" { Text "E:/数字逻辑/counterx/counterx.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "counterx " "Info: Elaborating entity \"counterx\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt\[0\]~12 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt\[0\]~12\"" {  } { { "counterx.vhd" "cnt\[0\]~12" { Text "E:/数字逻辑/counterx/counterx.vhd" 19 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "16 " "Info: Implemented 16 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "4 " "Info: Implemented 4 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 27 03:08:24 2006 " "Info: Processing ended: Sat May 27 03:08:24 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}