counterx.vhd

通过VHDL语言编写的计数器程序,可以在一吗器显示管上分段显示小时,分,秒,并且可以分别清零

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counterx IS
PORT
  (
   d:IN INTEGER RANGE 0 TO 15;
   clk:IN STD_LOGIC;
   clear:IN STD_LOGIC;
   ld:IN STD_LOGIC;
   enable:IN STD_LOGIC;
   qa:OUT INTEGER RANGE 0 TO 15
  );
END counterx;
ARCHITECTURE a OF counterx IS
BEGIN
  PROCESS (clk)
    VARIABLE cnt:INTEGER RANGE 0 TO 15;
  BEGIN
    IF(clk'EVENT AND clk='1')THEN
      IF clear='0' THEN
         cnt :=0;
      ELSE
         IF ld='0' THEN
            cnt :=d;
         ELSE
            IF enable='1' THEN
               cnt:=cnt+1;
            END IF;
         END IF;
      END IF;
    END IF;
    qa<=cnt;
  END PROCESS;
END a;