📄 counterx.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--C1_q[0] is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr
C1_q[0]_lut_out = ((enable $ C1_q[0] & ld) # (d[0] & !ld)) & clear;
C1_q[0] = DFFEA(C1_q[0]_lut_out, clk, , , , , );
--C1L11Q is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr
C1L11Q = C1_q[0];
--C1L3 is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr
C1L3 = CARRY(C1_q[0]);
--C1_q[1] is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr
C1_q[1]_lut_out = ((C1_q[1] $ (enable & C1L3) & ld) # (d[1] & !ld)) & clear;
C1_q[1] = DFFEA(C1_q[1]_lut_out, clk, , , , , );
--C1L31Q is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr
C1L31Q = C1_q[1];
--C1L5 is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr
C1L5 = CARRY(C1_q[1] & (C1L3));
--C1_q[2] is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr
C1_q[2]_lut_out = ((C1_q[2] $ (enable & C1L5) & ld) # (d[2] & !ld)) & clear;
C1_q[2] = DFFEA(C1_q[2]_lut_out, clk, , , , , );
--C1L51Q is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr
C1L51Q = C1_q[2];
--C1L7 is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr
C1L7 = CARRY(C1_q[2] & (C1L5));
--C1_q[3] is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr
C1_q[3]_lut_out = ((C1_q[3] $ (enable & C1L7) & ld) # (d[3] & !ld)) & clear;
C1_q[3] = DFFEA(C1_q[3]_lut_out, clk, , , , , );
--C1L71Q is lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr
C1L71Q = C1_q[3];
--enable is enable
--operation mode is input
enable = INPUT();
--clear is clear
--operation mode is input
clear = INPUT();
--d[0] is d[0]
--operation mode is input
d[0] = INPUT();
--ld is ld
--operation mode is input
ld = INPUT();
--clk is clk
--operation mode is input
clk = INPUT();
--d[1] is d[1]
--operation mode is input
d[1] = INPUT();
--d[2] is d[2]
--operation mode is input
d[2] = INPUT();
--d[3] is d[3]
--operation mode is input
d[3] = INPUT();
--qa[0] is qa[0]
--operation mode is output
qa[0] = OUTPUT(C1_q[0]);
--qa[1] is qa[1]
--operation mode is output
qa[1] = OUTPUT(C1_q[1]);
--qa[2] is qa[2]
--operation mode is output
qa[2] = OUTPUT(C1_q[2]);
--qa[3] is qa[3]
--operation mode is output
qa[3] = OUTPUT(C1_q[3]);
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