📄 lp_tx_stratix.map.rpt
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; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2 processors ; 0.0% ;
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+
; tx_pll.v ; yes ; User Wizard-Generated File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/tx_pll.v ;
; lp_tx_top_stratix.v ; yes ; User Verilog HDL File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v ;
; ddr_clk.v ; yes ; User Verilog HDL File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/ddr_clk.v ;
; ../../../source/verilog/lp_tx.v ; yes ; User Verilog HDL File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v ;
; altpll.tdf ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altpll.tdf ;
; aglobal111.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/aglobal111.inc ;
; stratix_pll.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/cycloneii_pll.inc ;
; dcfifo.tdf ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/dcfifo.tdf ;
; lpm_counter.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_counter.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; altdpram.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altdpram.inc ;
; a_graycounter.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/a_graycounter.inc ;
; a_fefifo.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/a_fefifo.inc ;
; a_gray2bin.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/a_gray2bin.inc ;
; dffpipe.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/dffpipe.inc ;
; alt_sync_fifo.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/alt_sync_fifo.inc ;
; lpm_compare.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_compare.inc ;
; altsyncram_fifo.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altsyncram_fifo.inc ;
; db/dcfifo_edn1.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/dcfifo_edn1.tdf ;
; db/alt_sync_fifo_1ck.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/alt_sync_fifo_1ck.tdf ;
; db/dpram_u441.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/dpram_u441.tdf ;
; db/altsyncram_arh1.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/altsyncram_arh1.tdf ;
; db/add_sub_pf8.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/add_sub_pf8.tdf ;
; db/add_sub_v08.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/add_sub_v08.tdf ;
; db/cntr_aua.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/cntr_aua.tdf ;
; altddio_out.tdf ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altddio_out.tdf ;
; stratix_ddio.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratix_ddio.inc ;
; cyclone_ddio.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/cyclone_ddio.inc ;
; lpm_mux.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_mux.inc ;
; stratix_lcell.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratix_lcell.inc ;
; stratix_ddio_out.v ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratix_ddio_out.v ;
; stratix_ddio_out_no_areset.v ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratix_ddio_out_no_areset.v ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------------------------+
; Total logic elements ; 150 ;
; -- Combinational with no register ; 28 ;
; -- Register only ; 35 ;
; -- Combinational with a register ; 87 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 10 ;
; -- 3 input functions ; 75 ;
; -- 2 input functions ; 29 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 107 ;
; -- arithmetic mode ; 43 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 8 ;
; -- asynchronous clear/load mode ; 122 ;
; ; ;
; Total registers ; 137 ;
; Total logic cells in carry chains ; 51 ;
; Virtual pins ; 39 ;
; I/O pins ; 10 ;
; Total memory bits ; 528 ;
; Total PLLs ; 1 ;
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