lp_tx_stratix.map.rpt

altera fpga 和ts201的linkport接口设计

Analysis & Synthesis report for lp_tx_stratix
Sat Apr 07 15:14:26 2012
Quartus II 32-bit Version 11.1 Build 173 11/01/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. General Register Statistics
 11. Inverted Register Statistics
 12. Source assignments for lp_tx:lp_tx|dcfifo:tx_fifo
 13. Source assignments for lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_edn1:auto_generated
 14. Source assignments for lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_edn1:auto_generated|alt_sync_fifo_1ck:sync_fifo|dpram_u441:dpram4|altsyncram_arh1:altsyncram13
 15. Source assignments for lp_tx:lp_tx|altddio_out:lp_tx_data_3
 16. Source assignments for lp_tx:lp_tx|altddio_out:lp_tx_data_2
 17. Source assignments for lp_tx:lp_tx|altddio_out:lp_tx_data_1
 18. Source assignments for lp_tx:lp_tx|altddio_out:lp_tx_data_0
 19. Source assignments for lp_tx:lp_tx|ddr_clk:lp_tx_clk|altddio_out:lp_tx_clk
 20. Parameter Settings for User Entity Instance: tx_pll:tx_pll|altpll:altpll_component
 21. Parameter Settings for User Entity Instance: lp_tx:lp_tx
 22. Parameter Settings for User Entity Instance: lp_tx:lp_tx|dcfifo:tx_fifo
 23. Parameter Settings for User Entity Instance: lp_tx:lp_tx|altddio_out:lp_tx_data_3
 24. Parameter Settings for User Entity Instance: lp_tx:lp_tx|altddio_out:lp_tx_data_2
 25. Parameter Settings for User Entity Instance: lp_tx:lp_tx|altddio_out:lp_tx_data_1
 26. Parameter Settings for User Entity Instance: lp_tx:lp_tx|altddio_out:lp_tx_data_0
 27. Parameter Settings for User Entity Instance: lp_tx:lp_tx|ddr_clk:lp_tx_clk|altddio_out:lp_tx_clk
 28. altpll Parameter Settings by Entity Instance
 29. dcfifo Parameter Settings by Entity Instance
 30. Port Connectivity Checks: "tx_pll:tx_pll"
 31. Elapsed Time Per Partition
 32. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                            ;
+-----------------------------+-------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Apr 07 15:14:26 2012     ;
; Quartus II 32-bit Version   ; 11.1 Build 173 11/01/2011 SJ Full Version ;
; Revision Name               ; lp_tx_stratix                             ;
; Top-level Entity Name       ; lp_tx_top_stratix                         ;
; Family                      ; Stratix                                   ;
; Total logic elements        ; 150                                       ;
; Total pins                  ; 10                                        ;
; Total virtual pins          ; 39                                        ;
; Total memory bits           ; 528                                       ;
; DSP block 9-bit elements    ; 0                                         ;
; Total PLLs                  ; 1                                         ;
; Total DLLs                  ; 0                                         ;
+-----------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP1S10F484C5       ;                    ;
; Top-level entity name                                                      ; lp_tx_top_stratix  ; lp_tx_stratix      ;
; Family name                                                                ; Stratix            ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;