cpu_system.txt

UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。

-- Structural description of a Microprocessor System
-- dowload from: www.fpga.com.cn & www.pld.com.cn

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY cpudemo IS
END cpudemo;

ARCHITECTURE version1 OF cpudemo IS

COMPONENT rom256x8 
        PORT(address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                csbar, oebar : IN STD_LOGIC;
                data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

COMPONENT ram16x8 
        PORT(address : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                csbar, oebar, webar : IN STD_LOGIC;
                data : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

COMPONENT cpu
        GENERIC(cycle_time : TIME := 200 ns); --must be divisible by 8
        PORT(reset : IN std_logic;
                memrd, memwr : OUT std_logic;
                address : OUT std_logic_vector(11 DOWNTO 0);
                data : INOUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;

SIGNAL reset, memrd, memwr, romenable, ramenable : std_logic;
SIGNAL address : std_logic_vector(11 DOWNTO 0);
SIGNAL data : std_logic_vector(7 DOWNTO 0);

--selecting the rom architecture (program) for simulation
FOR rom : rom256x8 USE ENTITY work.rom256x8(version2);

BEGIN

processor : cpu PORT MAP(reset, memrd, memwr, address, data);

rom : rom256x8 PORT MAP(address(7 DOWNTO 0), romenable, memrd, data);

ram : ram16x8 PORT MAP(address(3 DOWNTO 0), ramenable, memrd, memwr, data);

--memory address decoding ,rom is at bottom of address space
--ram is situated at address $100
romenable <= '0' WHEN (address(11 DOWNTO 8) = "0000") ELSE '1';
ramenable <= '0' WHEN (address(11 DOWNTO 4) = "00010000") ELSE '1';

END version1;