conversion_altera.vhd

来自「UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实」· VHDL 代码 · 共 20 行

-- MAX+plus II VHDL Example
-- Conversion Function
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn 

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY adder IS
	PORT (op1, op2		: IN  UNSIGNED(7 downto 0);
		   result		: OUT INTEGER);
END adder;

ARCHITECTURE maxpld OF adder IS
BEGIN
	result <= CONV_INTEGER(op1 + op2);
END maxpld;