condsig.vhd

来自「UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实」· VHDL 代码 · 共 23 行

-- MAX+plus II VHDL Example
-- Conditional Signal Assignment
-- Copyright (c) 1994 Altera Corporation

Library IEEE ;
use IEEE.std_logic_1164.all ;

ENTITY condsig IS
	PORT
	(
		input0, input1, sel	: IN  BIT;
		output				: OUT BIT
	);
END condsig;

ARCHITECTURE maxpld OF condsig IS
BEGIN

	output <= input0 WHEN sel = '0' ELSE input1;
		
END maxpld;