two_d_filter.vt

FIR FILTER verilog code

// Copyright (C) 1991-2002 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "12/28/2001 11:29:02"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          two_d_filter
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module two_d_filter_vlg_vec_tst();
// constants                                           
// general purpose registers                               
reg t__reg__aclr;
reg t__reg__clk;
reg t__reg__clken;
reg [8:0] t__reg__coef1_1;
reg [8:0] t__reg__coef1_2;
reg [8:0] t__reg__coef1_3;
reg [8:0] t__reg__coef2_1;
reg [8:0] t__reg__coef2_2;
reg [8:0] t__reg__coef2_3;
reg [8:0] t__reg__coef3_1;
reg [8:0] t__reg__coef3_2;
reg [8:0] t__reg__coef3_3;
reg [7:0] t__reg__data;
reg t__reg__data_valid;
// wires                                               
wire t__wire__aclr;
wire t__wire__clk;
wire t__wire__clken;
wire [8:0] t__wire__coef1_1;
wire [8:0] t__wire__coef1_2;
wire [8:0] t__wire__coef1_3;
wire [8:0] t__wire__coef2_1;
wire [8:0] t__wire__coef2_2;
wire [8:0] t__wire__coef2_3;
wire [8:0] t__wire__coef3_1;
wire [8:0] t__wire__coef3_2;
wire [8:0] t__wire__coef3_3;
wire [7:0] t__wire__data;
wire t__wire__data_valid;
wire [20:0] t__wire__result;
wire [7:0] t__wire__row1_1;
wire [7:0] t__wire__row1_2;
wire [7:0] t__wire__row1_3;
wire [7:0] t__wire__row2_1;
wire [7:0] t__wire__row2_2;
wire [7:0] t__wire__row2_3;
wire [7:0] t__wire__row3_1;
wire [7:0] t__wire__row3_2;
wire [7:0] t__wire__row3_3;

// assign statements (if any)                          
assign {t__wire__aclr,t__wire__clk,t__wire__clken,t__wire__coef1_1,t__wire__coef1_2,t__wire__coef1_3,t__wire__coef2_1,t__wire__coef2_2,t__wire__coef2_3,t__wire__coef3_1,t__wire__coef3_2,t__wire__coef3_3,t__wire__data,t__wire__data_valid} = {t__reg__aclr,t__reg__clk,t__reg__clken,t__reg__coef1_1,t__reg__coef1_2,t__reg__coef1_3,t__reg__coef2_1,t__reg__coef2_2,t__reg__coef2_3,t__reg__coef3_1,t__reg__coef3_2,t__reg__coef3_3,t__reg__data,t__reg__data_valid};
two_d_filter tb (
// port map - connection between master ports and signals/registers   
.aclr(t__wire__aclr),.clk(t__wire__clk),.clken(t__wire__clken),.coef1_1(t__wire__coef1_1),.coef1_2(t__wire__coef1_2),.coef1_3(t__wire__coef1_3),.coef2_1(t__wire__coef2_1),.coef2_2(t__wire__coef2_2),.coef2_3(t__wire__coef2_3),.coef3_1(t__wire__coef3_1),.coef3_2(t__wire__coef3_2),.coef3_3(t__wire__coef3_3),.data(t__wire__data),.data_valid(t__wire__data_valid),.result(t__wire__result),.row1_1(t__wire__row1_1),.row1_2(t__wire__row1_2),.row1_3(t__wire__row1_3),.row2_1(t__wire__row2_1),.row2_2(t__wire__row2_2),.row2_3(t__wire__row2_3),.row3_1(t__wire__row3_1),.row3_2(t__wire__row3_2),.row3_3(t__wire__row3_3));
// aclr
initial
begin
	t__reg__aclr = "0";
	t__reg__aclr = #423 "1";
	t__reg__aclr = #78325 "0";
end 
// clk
always
begin
	t__reg__clk = "0";
	t__reg__clk = #20000 "1";
	#20000;
end 
// clken
initial
begin
	t__reg__clken = "1";
	t__reg__clken = #423 "0";
	t__reg__clken = #79595 "1";
end 
// coef1_1[ 0 ]
initial
begin
	t__reg__coef1_1[0] = "1";
end 
// coef1_2[ 8 ]
always
begin
	t__reg__coef1_2[8] = "0";
	#4000000;
end 
// coef1_2[ 7 ]
always
begin
	t__reg__coef1_2[7] = "0";
	#4000000;
end 
// coef1_2[ 6 ]
always
begin
	t__reg__coef1_2[6] = "0";
	#4000000;
end 
// coef1_2[ 5 ]
always
begin
	t__reg__coef1_2[5] = "0";
	#4000000;
end 
// coef1_2[ 4 ]
always
begin
	t__reg__coef1_2[4] = "0";
	#4000000;
end 
// coef1_2[ 3 ]
always
begin
	t__reg__coef1_2[3] = "0";
	#4000000;
end 
// coef1_2[ 2 ]
always
begin
	t__reg__coef1_2[2] = "0";
	#4000000;
end 
// coef1_2[ 1 ]
always
begin
	t__reg__coef1_2[1] = "0";
	#4000000;
end 
// coef1_2[ 0 ]
always
begin
	t__reg__coef1_2[0] = "1";
	#4000000;
end 
// coef1_3[ 8 ]
always
begin
	t__reg__coef1_3[8] = "0";
	#4000000;
end 
// coef1_3[ 7 ]
always
begin
	t__reg__coef1_3[7] = "0";
	#4000000;
end 
// coef1_3[ 6 ]
always
begin
	t__reg__coef1_3[6] = "0";
	#4000000;
end 
// coef1_3[ 5 ]
always
begin
	t__reg__coef1_3[5] = "0";
	#4000000;
end 
// coef1_3[ 4 ]
always
begin
	t__reg__coef1_3[4] = "0";
	#4000000;
end 
// coef1_3[ 3 ]
always
begin
	t__reg__coef1_3[3] = "0";
	#4000000;
end 
// coef1_3[ 2 ]
always
begin
	t__reg__coef1_3[2] = "0";
	#4000000;
end 
// coef1_3[ 1 ]
always
begin
	t__reg__coef1_3[1] = "0";
	#4000000;
end 
// coef1_3[ 0 ]
always
begin
	t__reg__coef1_3[0] = "1";
	#4000000;
end 
// coef2_1[ 8 ]
always
begin
	t__reg__coef2_1[8] = "0";
	#4000000;
end 
// coef2_1[ 7 ]
always
begin
	t__reg__coef2_1[7] = "0";
	#4000000;
end 
// coef2_1[ 6 ]
always
begin
	t__reg__coef2_1[6] = "0";
	#4000000;
end 
// coef2_1[ 5 ]
always
begin
	t__reg__coef2_1[5] = "0";
	#4000000;
end 
// coef2_1[ 4 ]
always
begin
	t__reg__coef2_1[4] = "0";
	#4000000;
end 
// coef2_1[ 3 ]
always
begin
	t__reg__coef2_1[3] = "0";
	#4000000;
end 
// coef2_1[ 2 ]
always
begin
	t__reg__coef2_1[2] = "0";
	#4000000;
end 
// coef2_1[ 1 ]
always
begin
	t__reg__coef2_1[1] = "0";
	#4000000;
end 
// coef2_1[ 0 ]
always
begin
	t__reg__coef2_1[0] = "1";
	#4000000;
end 
// coef2_2[ 8 ]
always
begin
	t__reg__coef2_2[8] = "0";
	#4000000;
end 
// coef2_2[ 7 ]
always
begin
	t__reg__coef2_2[7] = "0";
	#4000000;
end 
// coef2_2[ 6 ]
always
begin
	t__reg__coef2_2[6] = "0";
	#4000000;
end 
// coef2_2[ 5 ]
always
begin
	t__reg__coef2_2[5] = "0";
	#4000000;
end 
// coef2_2[ 4 ]
always
begin
	t__reg__coef2_2[4] = "0";
	#4000000;
end 
// coef2_2[ 3 ]
always
begin
	t__reg__coef2_2[3] = "0";
	#4000000;
end 
// coef2_2[ 2 ]
always
begin
	t__reg__coef2_2[2] = "0";
	#4000000;
end 
// coef2_2[ 1 ]
always
begin
	t__reg__coef2_2[1] = "0";
	#4000000;
end 
// coef2_2[ 0 ]
always
begin
	t__reg__coef2_2[0] = "1";
	#4000000;
end 
// coef2_3[ 8 ]
always
begin
	t__reg__coef2_3[8] = "0";
	#4000000;
end 
// coef2_3[ 7 ]
always
begin
	t__reg__coef2_3[7] = "0";
	#4000000;
end 
// coef2_3[ 6 ]
always
begin
	t__reg__coef2_3[6] = "0";
	#4000000;
end 
// coef2_3[ 5 ]
always
begin
	t__reg__coef2_3[5] = "0";
	#4000000;
end 
// coef2_3[ 4 ]
always
begin
	t__reg__coef2_3[4] = "0";
	#4000000;
end 
// coef2_3[ 3 ]
always
begin
	t__reg__coef2_3[3] = "0";
	#4000000;
end 
// coef2_3[ 2 ]
always
begin
	t__reg__coef2_3[2] = "0";
	#4000000;
end 
// coef2_3[ 1 ]
always
begin
	t__reg__coef2_3[1] = "0";
	#4000000;
end 
// coef2_3[ 0 ]
always
begin
	t__reg__coef2_3[0] = "1";
	#4000000;
end 
// coef3_1[ 8 ]
always
begin
	t__reg__coef3_1[8] = "0";
	#4000000;
end 
// coef3_1[ 7 ]
always
begin
	t__reg__coef3_1[7] = "0";
	#4000000;
end 
// coef3_1[ 6 ]
always
begin
	t__reg__coef3_1[6] = "0";
	#4000000;
end 
// coef3_1[ 5 ]
always
begin
	t__reg__coef3_1[5] = "0";
	#4000000;
end 
// coef3_1[ 4 ]
always
begin
	t__reg__coef3_1[4] = "0";
	#4000000;
end 
// coef3_1[ 3 ]
always
begin
	t__reg__coef3_1[3] = "0";
	#4000000;
end 
// coef3_1[ 2 ]
always
begin
	t__reg__coef3_1[2] = "0";
	#4000000;
end 
// coef3_1[ 1 ]
always
begin
	t__reg__coef3_1[1] = "0";
	#4000000;
end 
// coef3_1[ 0 ]
always
begin
	t__reg__coef3_1[0] = "1";
	#4000000;
end 
// coef3_2[ 8 ]
always
begin
	t__reg__coef3_2[8] = "0";
	#4000000;
end 
// coef3_2[ 7 ]
always
begin
	t__reg__coef3_2[7] = "0";
	#4000000;
end 
// coef3_2[ 6 ]
always
begin
	t__reg__coef3_2[6] = "0";
	#4000000;
end 
// coef3_2[ 5 ]
always
begin
	t__reg__coef3_2[5] = "0";
	#4000000;
end 
// coef3_2[ 4 ]
always
begin
	t__reg__coef3_2[4] = "0";
	#4000000;
end 
// coef3_2[ 3 ]
always
begin
	t__reg__coef3_2[3] = "0";
	#4000000;
end 
// coef3_2[ 2 ]
always
begin
	t__reg__coef3_2[2] = "0";
	#4000000;
end 
// coef3_2[ 1 ]
always
begin
	t__reg__coef3_2[1] = "0";
	#4000000;
end 
// coef3_2[ 0 ]
always
begin
	t__reg__coef3_2[0] = "1";
	#4000000;
end 
// coef3_3[ 8 ]
always
begin
	t__reg__coef3_3[8] = "0";
	#4000000;
end 
// coef3_3[ 7 ]
always
begin
	t__reg__coef3_3[7] = "0";
	#4000000;
end 
// coef3_3[ 6 ]
always
begin
	t__reg__coef3_3[6] = "0";
	#4000000;
end 
// coef3_3[ 5 ]
always
begin
	t__reg__coef3_3[5] = "0";
	#4000000;
end 
// coef3_3[ 4 ]
always
begin
	t__reg__coef3_3[4] = "0";
	#4000000;
end 
// coef3_3[ 3 ]
always
begin
	t__reg__coef3_3[3] = "0";
	#4000000;
end 
// coef3_3[ 2 ]
always
begin
	t__reg__coef3_3[2] = "0";
	#4000000;
end 
// coef3_3[ 1 ]
always
begin
	t__reg__coef3_3[1] = "0";
	#4000000;
end 
// coef3_3[ 0 ]
always
begin
	t__reg__coef3_3[0] = "1";
	#4000000;
end 
// data[ 7 ]
initial
begin
	t__reg__data[7] = "0";
end 
// data[ 6 ]
initial
begin
	t__reg__data[6] = "0";
	t__reg__data[6] = #2713909 "1";
	t__reg__data[6] = #40793 "0";
end 
// data[ 5 ]
initial
begin
	t__reg__data[5] = "0";
	t__reg__data[5] = #1433909 "1";
	t__reg__data[5] = #1280000 "0";
end 
// data[ 4 ]
initial
begin
	t__reg__data[4] = "0";
	t__reg__data[4] = #793909 "1";
	t__reg__data[4] = #640000 "0";
	t__reg__data[4] = #640000 "1";
	t__reg__data[4] = #640000 "0";
end 
// data[ 3 ]
initial
begin
	t__reg__data[3] = "0";
	t__reg__data[3] = #473909 "1";
	# 320000;
	repeat(3)
	begin
		t__reg__data[3] = "0";
		t__reg__data[3] = #320000 "1";
		# 320000;
	end
	t__reg__data[3] = "0";
end 
// data[ 2 ]
initial
begin
	t__reg__data[2] = "0";
	t__reg__data[2] = #313909 "1";
	# 160000;
	repeat(7)
	begin
		t__reg__data[2] = "0";
		t__reg__data[2] = #160000 "1";
		# 160000;
	end
	t__reg__data[2] = "0";
end 
// data[ 1 ]
initial
begin
	t__reg__data[1] = "0";
	t__reg__data[1] = #233909 "1";
	# 80000;
	repeat(15)
	begin
		t__reg__data[1] = "0";
		t__reg__data[1] = #80000 "1";
		# 80000;
	end
	t__reg__data[1] = "0";
end 
// data[ 0 ]
initial
begin
	t__reg__data[0] = "0";
	t__reg__data[0] = #193909 "1";
	# 40000;
	repeat(31)
	begin
		t__reg__data[0] = "0";
		t__reg__data[0] = #40000 "1";
		# 40000;
	end
	t__reg__data[0] = "0";
	t__reg__data[0] = #40000 "1";
	t__reg__data[0] = #793 "0";
end 
// data_valid
initial
begin
	t__reg__data_valid = "0";
	t__reg__data_valid = #194935 "1";
	t__reg__data_valid = #2555065 "0";
end 
initial 
begin 
#4000000 $stop;
end 
endmodule