vga_test1.v

在显示器上显示汉字,在FPGA上实现,使用Verilog HDL 设计,完全可是直接使用

////////////////////////////////////////////////////////////////////////////////
// *****************************************************************************
// *  RICHIC CONFIDENTIAL PROPRIETARY NOTE                                     *
// *                                                                           *
// *  This software contains information confidential and proprietary to       *
// *  RicHic Inc.It shall not be reproduced in whole or in part or transferred *
// *  to other documents, or disclosed to third parties, or used for any       *
// *  purpose other than that for which it was obtained, without the prior     *
// *  written consent of RicHic Inc.                                           *
// *             (c) 2003, 2004, 2005 RicHic Inc.                              *
// *                All rights reserved                                        * 
// *****************************************************************************
//
// (C) 2004 [e-mail];     [e-mail]
//     http://www.richic.com
//
////////////////////////////////////////////////////////////////////////////////

module vga_test1(
    clk         ,
    rst_n       , 
    vga_hsync   , 
    vga_vsync   , 

    vga_red0    , 
    vga_red1    , 
    vga_green0  , 
    vga_green1  , 
    vga_blue0   , 
    vga_blue1
    );

input 	clk;
input   rst_n ;// synthesis attribute clock_buffer of rst_n is ibufg;
output 	vga_hsync;
output  vga_vsync; // sync signals for monitor
output 	vga_red0, vga_green0, vga_blue0, vga_red1, vga_green1, vga_blue1;

wire            hsync;
wire            vsync;
wire            valid;        
wire    [9:0]   x_cnt;
wire    [9:0]   y_cnt;

wire    [9:0]   char_sel;
wire    [15:0]  char;
        
wire    [9:0]   xpos    ;//[0...799]
wire    [9:0]   ypos    ;//[0...599]
reg     color;
assign  xpos    =   x_cnt - 10'd180;
assign  ypos    =   y_cnt - 10'd35;        
                

sync_gen_50m sync_gen_50m_int
    (
    .rst_n   (rst_n  ),
    .clk     (clk    ),
    
    .hsync   (hsync  ),
    .vsync   (vsync  ),
    .valid   (valid  ),
    .x_cnt   (x_cnt  ),
    .y_cnt   (y_cnt  )
    );        
        
wire    table0 = (( ypos > 10'd140 && ypos < 10'd460 )&&( xpos > 10'd160 && xpos < 10'd640 ));

wire    line0 = (( ypos == 10'd140 || ypos == 10'd460 ) && ( xpos > 10'd160 && xpos < 10'd640 )||
                 ( xpos == 10'd160 || xpos == 10'd640 ) && ( ypos > 10'd140 && ypos < 10'd460 ));

wire    word0 = ((xpos > 10'd204) && (xpos < 10'd588) &&
                 (ypos > 10'd96) && (ypos < 10'd128));
wire    word = word0 && color;

assign vga_red0   = valid ? (word ? 1'b1 : (line0 ? 1'b1 : (table0? 1'b0 : 1'b0 ))) : 1'b0;
assign vga_red1   = valid ? (word ? 1'b1 : (line0 ? 1'b1 : (table0? 1'b0 : 1'b0 ))) : 1'b0;
assign vga_green0 = valid ? (word ? 1'b0 : (line0 ? 1'b1 : (table0? 1'b0 : 1'b0 ))) : 1'b0;
assign vga_green1 = valid ? (word ? 1'b0 : (line0 ? 1'b1 : (table0? 1'b0 : 1'b0 ))) : 1'b0;
assign vga_blue0  = valid ? (word ? 1'b0 : (line0 ? 1'b1 : (table0? 1'b0 : 1'b1 ))) : 1'b0;
assign vga_blue1  = valid ? (word ? 1'b0 : (line0 ? 1'b1 : (table0? 1'b0 : 1'b1 ))) : 1'b0;
assign  vga_hsync   =   hsync;
assign  vga_vsync   =   vsync;

assign  char_sel = xpos -10'd204 ;
char_rom char_rom_inst(
    .addr   ({char_sel[9:5],ypos[4:1]}), 
    .data   (char));

always @(char_sel[4:1] or char)
    begin  	
	    case (char_sel[4:1])
	      4'h0 : color = char[15];
	      4'h1 : color = char[14];
	      4'h2 : color = char[13];
	      4'h3 : color = char[12];
	      4'h4 : color = char[11];
	      4'h5 : color = char[10];
	      4'h6 : color = char[9];
	      4'h7 : color = char[8];	 	      	 	      
	      4'h8 : color = char[7];
	      4'h9 : color = char[6];
	      4'hA : color = char[5];
	      4'hB : color = char[4];
	      4'hC : color = char[3];
	      4'hD : color = char[2];
	      4'hE : color = char[1];
	      4'hF : color = char[0];	 	      	 	      
	    endcase
    end  
endmodule